Photovoltaic module including integrated photovoltaic cells

ABSTRACT

A photovoltaic module and its manufacturing method. The module includes a first support wafer made of sintered silicon and a second layer of single-crystal silicon.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation in part of pending U.S. application Ser. No. 12/954,273, filed Nov. 24, 2010, which is a continuation in part of U.S. application Ser. No. 12/760,086, filed Apr. 14, 2010, now issued U.S. Pat. No. 8,405,183, which is a continuation in part of U.S. application Ser. No. 12/184,703, filed Aug. 1, 2008, now issued U.S. Pat. No. 8,192,648, which is a continuation in part of U.S. application Ser. No. 10/552,548, filed Oct. 12, 2005, now issued U.S. Pat. No. 8,105,293, entitled SINTERED SEMICONDUCTOR MATERIAL, which is the national stage application under 35 U.S.C. §371 of the International Application No. PCT/FR2004/050151 and claims the benefit of French Application No. 03/04676, filed Apr. 14, 2003, International Application No. PCT/FR2004/050151, filed Apr. 9, 2004, and French Application No. 09/58441, filed on Nov. 27, 2009, the entire disclosures of which are incorporated herein by reference in their entireties.

FIELD OF THE INVENTION

The present invention relates to the field of semiconductors, and in particular, but not exclusively, of semiconductor materials usable to form photovoltaic cells, also called photocells, and photovoltaic modules, also called solar panels.

BACKGROUND

FIG. 1 shows a conventional photovoltaic cell 1. Photovoltaic cell 1 comprises a planar semiconductor material 3. Material 3, generally made of polysilicon, comprises three areas of different doping. A thick central area 3 a is lightly P-type doped. An upper area 3 b is N-type doped, and possibly overdoped at its surface. A lower area 3 c is heavily P-type doped (P+). A conductive comb 5 is placed above area 3 b, intended to be exposed to light. An aluminum layer 6 covers the lower surface of the cell. Comb 5 and layer 6 are both intended to transmit the photovoltaic current and are connected to the + and − terminals, not shown, of the cell. An antireflection layer, not shown, is preferably placed on area 3 b and comb 5 to limit the reflection of light rays at the photocell surface.

Material 3 conventional originates from a polysilicon bar obtained from a silicon melt. The bar is sawn to obtain wafers which are then doped to obtain material 3. This manufacturing method, close to the single-crystal silicon wafer manufacturing method, is expensive and limits the possible wafer dimensions.

SUMMARY

The inventor has disclosed in a conference in Munich (17^(th) European Photovoltaic Solar Energy Conference and Exhibition, Munich, 21-26 Oct. 2001) a method for manufacturing polysilicon wafers by sintering of silicon powders. In this method, silicon powders of 5 μm or 20 μm are placed between the plates of a press. The assembly is compressed with a pressure P ranging between 70 MPa (700 bars) and 900 MPa (9,000 bars). Then, the compacted layer is introduced into a sintering furnace, where it is heated up to a temperature T ranging between 950° C. and 1050° C. The sintering, which enables growth of bridges between the grains and stiffening of the material, has been performed at the indicated temperatures for a time range from two to eight hours, under a low argon pressure (100 Pa).

The obtained materials have a sufficient mechanical strength to be able to be handled. However, their porosity is high, above 15%. Further, the grain size is small, since the size of said grains has not substantially increased during the processing. The mobility-lifetime product of the minority carriers is low, on the order of 10-7 cm2V-1 (10-11 m2V-1 in the international system). The obtained materials are unusable in the photovoltaic field. For example, due to the high porosity, it is impossible to dope a specific area of the material, the dopants migrating through the porosity channels and spreading everywhere inside the material. As to the mobility-lifetime product of the minority carriers, values at least one thousand times greater are required for the material to be used in a photocell. Further, the surface of the obtained materials is uncontrolled and rough. Such a surface state prevents the provision of surface junctions, necessary poor, in particular because of significant leakage currents.

An object of the present invention is to form a semiconductor material or component by sintering of semiconductor powders usable in the electronic field, especially in the photovoltaic field.

Another object of the present invention is to form a semiconductor material by sintering of semiconductor powders exhibiting a low roughness and/or a controlled texturation surface condition.

To achieve these objects, the present invention provides a method for forming a semiconductor material from powders comprising at least one component belonging to the group formed by the elements of column IV of the Mendeleiev table and their alloys. The method comprises a step of compression of said powders and a thermal processing step such that part at least of the powders is melted or made viscous.

According to an embodiment of the present invention, the compression and thermal processing steps are simultaneous.

According to an embodiment of the present invention, the thermal processing is such that only powders belonging to a specific area of the material are melted or made viscous.

According to an embodiment of the present invention, the powders comprise silicon powders and powders of at least another component, the thermal processing being such that the silicon is not melted and that at least one of the other components is melted or made viscous.

According to an embodiment of the present invention, the powders comprise doped semiconductor powders and undoped semiconductor powders, the thermal processing being such that only the doped powders are melted.

According to an embodiment of the present invention, the compression step is preceded by a step consisting of placing powders on a plate, the powders being different as to their nature, their granulometry, and/or their doping according to their location on the plate.

According to an embodiment of the present invention, in the compression step, said powders are pressed between plates having a surface capable of texturizing the surface of the material.

The present invention also provides a semiconductor material obtained at least partially by compression and thermal processing of powders comprising at least two distinct areas formed of distinct components belonging to the group formed by the elements of column IV of the Mendeleiev table and the alloys thereof.

According to an embodiment of the present invention, said areas are superposed.

The present invention also provides a structure or component formed of one or comprising at least one semiconductor material comprising grains and/or aggregates exhibiting energy gaps of different value.

The present invention also provides a method for forming a material from a source material comprising the following steps:

a) grinding the source material to get powders if the source material is not already in the form of powders;

b) sintering the powders with at least one compression step and one thermal processing step; and

c) purifying the material with a gas flow, the gas flow passing through the porosity channels of the material.

According to an embodiment of the present invention, the gas is a non reactive gas.

According to an embodiment of the present invention, the gas comprises at least one reactive gas which reacts with determined impurities of the material in order to form volatile components which are carried out of the material by the gas flow.

According to an embodiment of the present invention, the gas comprises hydrogen or an element of the halogen family, like fluorine, chlorine or bromine.

According to an embodiment of the present invention, the gas is a mixture of a non reactive carrier gas and at least one reactive gas.

According to an embodiment of the present invention, the gas flow is produced by pumping, the gas pressure being the atmospheric pressure or a pressure comprised between 1 hectopascal and the atmospheric pressure.

According to an embodiment of the present invention, the gas has a pressure greater than one atmosphere.

According to an embodiment of the present invention, the purification step takes place after the sintering process, but before a liquid phase appears in the material if a liquid phase is needed.

According to an embodiment of the present invention, the purification step is simultaneous with at least one compression step and/or one thermal processing step.

According to an embodiment of the present invention, the sintering step comprises a hot pressing step.

According to an embodiment of the present invention, the sintering step comprises at least one cold compression step followed with at least one thermal processing step.

According to an embodiment of the present invention, the material is a semiconductor material which can be used in the photovoltaic, electronic and/or microelectronic filed.

According to an embodiment of the present invention, the material is a wafer.

According to an embodiment of the present invention, the wafer has a thickness comprised between 100 and 300 micrometers.

According to an embodiment of the present invention, the powders used in the sintering step are powders comprising at least one component belonging to the group formed by the elements of column IV of the Mendeleiev table and their alloys.

The present invention also provides a structure comprising a first layer made of sintered silicon powders and a second layer made of single-crystal silicon.

According to an embodiment of the present invention, the structure comprises a layer forming a diffusion barrier between the first and second layers.

According to an embodiment of the present invention, the structure comprises an insulating layer between the first and second layers.

According to an embodiment of the present invention, the insulating layer or the layer forming the diffusion barrier is a layer made of silica, silicon nitride and/or silicon carbide.

According to an embodiment of the present invention, the first layer has a thickness greater than 50 micrometers and/or the second layer has a thickness comprised between one and 50 micrometers.

According to an embodiment of the present invention, the layer forming a diffusion layer has a thickness lower than 10 nanometers and/or the thickness of the insulating layer has a thickness larger than 10 nanometers.

According to an embodiment of the present invention, the porosity channels of the structure comprise a doping element or a conductive material.

According to an embodiment of the present invention, holes pass through the first layer and the insulating layer if the insulating layer is present.

The present invention also provides an electronic structure comprising:

-   -   a first area comprising silicon grains having a size smaller         than 100 micrometers;     -   a second area superposed to the first area and comprising         silicon grains having a size greater than or equal to 100         micrometers, the first and second areas forming a support; and     -   one or several layers of an epitaxial semiconductor material on         the second area.

According to an embodiment of the present invention, the support has a doping concentration greater than 1018 atoms/cm3 obtained by means of dopants of a first and/or of a second type, and wherein the or at least one of the epitaxial layers has a doping concentration lower than 1018 atoms/cm3 obtained by means of dopants of the first and/or of the second type.

According to an embodiment of the present invention, the thickness of the epitaxial layer(s) is smaller than the size of the silicon grains of the second area.

According to an embodiment of the present invention, the structure comprises a first epitaxial layer adjacent to the support and doped with a dopant of same nature as that of the support and a second epitaxial layer thinner than the first layer, doped with a dopant of a different nature than that of the support.

According to an embodiment of the present invention, the structure comprises an epitaxial layer adjacent to the support and doped with a dopant of different nature than that of the support.

According to an embodiment of the present invention, the support comprises third areas with a doping of the first type alternating with fourth areas with a doping of the second type, and the epitaxial layer, doped with a dopant of the second type, comprises fifth doped areas of the first or of the second type, the doping of the fifth areas resulting from the diffusion of the dopants of the third and fourth areas.

According to an embodiment of the present invention, an epitaxial layer comprises several sub-layers of materials of different natures.

According to an embodiment of the present invention, the materials of the sub-layers are either pure silicon, or pure germanium, or a silicon and germanium alloy of formula SixGe1-x, x being a parameter that may range from 0 to 1, depending on the considered sub-layer.

According to an embodiment of the present invention, the first type of doping is a doping of N or N+ type and the second type of doping is a doping of P or P+ type.

According to an embodiment of the present invention, the thickness of the support is greater than 100 micrometers, the thickness of the first area ranging between a minimum thickness equal to zero and a maximum thickness equal to the thickness of the support minus 100 micrometers.

According to an embodiment of the present invention, the support is not planar and/or has any shape.

The present invention also provides a photovoltaic cell comprising an electronic structure as described above.

According to an embodiment of the present invention, the photovoltaic cell comprises an antireflection layer and/or ohmic contact areas arranged on the two cell surfaces or on a single surface of the cell.

The present invention also provides a photovoltaic module comprising a sintered silicon support comprising several integrated photovoltaic cells.

According to an embodiment of the present invention, the photovoltaic cells are insulated from one another by oxidized portions of the sintered silicon support.

According to an embodiment of the present invention, the oxidized portions extend from one surface to the other of the support.

According to an embodiment of the present invention, at least two photovoltaic cells are connected in series.

According to an embodiment of the present invention, each of the photovoltaic cells comprises a first heavily-doped area of a first type inside and/or on top of the support and a second area at least partly arranged on the first area, of a doping of the same type as the first area and less heavily doped than the first area, the first area defining a first terminal of the photovoltaic cell.

According to an embodiment of the present invention, each of the photovoltaic cells comprises a third doped area of a second type different from the first type and arranged on the second area, the third area defining a second terminal of the cell.

According to an embodiment of the present invention, each of the photovoltaic cells comprises a fourth heavily-doped area of a second type different from the first type and arranged under the second area, the fourth area defining a second terminal of the cell.

According to an embodiment of the present invention, the photovoltaic module comprises vias enabling to connect the cells from the rear surface of the support intended not to be exposed to sunlight.

According to an embodiment of the present invention, the photovoltaic module comprises an area comprising at least one electronic component or circuit other than a photovoltaic cell.

According to an embodiment of the present invention, the sintered silicon support is heavily doped of the P-type, and each photovoltaic cell on the support comprises a lightly doped layer of the type P coated with a doped layer of the type N, vias and/or metallizations enabling the connection of the cells in series and/or in parallel.

According to an embodiment of the present invention, the sintered silicon support is heavily doped of the N-type, and each photovoltaic cell on the support comprises a lightly doped layer of the type N coated with a doped layer of the type P, vias and/or metallizations enabling the connection of the cells in series and/or in parallel.

According to an embodiment of the present invention, the sintered silicon support is not doped, and each photovoltaic cell comprises a buried comb heavily doped of the type P, a buried comb heavily doped of the type N and an absorber lightly doped of the type P or of the type N.

According to an embodiment of the present invention, the connection in series and/or in parallel of the cells are provided by vias and/or metallizations at the rear surface of the support intended not to be exposed to sunlight.

According to an embodiment of the present invention, the width of the P doped buried comb is narrower than the width of the N doped buried comb when the absorber is doped with the P type, and wherein the width of the N doped buried comb is narrower than the width of the P doped buried comb when the absorber is doped with the N type.

According to an embodiment of the present invention, the photovoltaic cells have the shape of strips extending from one edge of the module to the other.

According to an embodiment of the present invention, the connections of the cells are only provided at the front surface of the module, intended to be exposed to sunlight.

The present invention also provides a method of manufacturing a photovoltaic module comprising a support comprising several integrated photovoltaic cells, the support being formed during a step of sintering of silicon powders.

According to an embodiment of the present invention, the method comprises the step of locally introducing an oxidizing agent into the support to make it locally insulating to form, in the support, areas electrically insulated from one another.

According to an embodiment of the present invention, the photovoltaic cells are formed on said areas electrically insulated from one another.

According to an embodiment of the present invention, the forming of the photovoltaic cells comprises the steps of:

a) forming a first heavily doped area, of a first type, inside and on top of the support, the first area defining a first terminal of the photovoltaic cell;

b) forming on the first area a second area having a doping of the same type as the first area and less heavily doped than the first area; and

c) forming on the second area a third doped area of a second type different from the first type, the third area defining a second terminal of the photovoltaic cell.

According to an embodiment of the present invention, the forming of the photovoltaic cells comprises the steps of:

a) forming a first heavily doped area, of a first type, inside and on top of the support, the first area defining a first terminal of the photovoltaic cell;

b) forming, inside and on top of the support, a second heavily-doped area of a second type different from the first type, adjacent to the first area and with no contact therewith, the second area defining a second terminal of the photovoltaic cell; and

c) forming on the first and second areas a third area having a doping of the same type as the first area and less heavily doped than the first area.

According to an embodiment of the present invention, the method comprises a step of connecting at least two photovoltaic cells in series.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features, and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, among which:

FIG. 1 shows a conventional photovoltaic cell;

FIG. 2 illustrates an embodiment of the method according to the present invention;

FIG. 3 shows a material according to the present invention;

FIG. 4 shows a structure according to the present invention;

FIGS. 5a and 5b illustrate other embodiments of the method according to the present invention;

FIGS. 6, 7A to 7C illustrate ways of doping a material according to the present invention;

FIGS. 8, 9, and 10 show materials according to the present invention;

FIG. 11 shows an assembly used by the method of the present invention;

FIG. 12 shows a device used for producing materials according to the present invention;

FIG. 13 shows a material according to the present invention;

FIGS. 14A, 14B, 14C and 14D show a process according to the present invention;

FIG. 15 shows a material according to the present invention;

FIG. 16 shows a material according to the present invention;

FIGS. 17 to 22 illustrate a method for forming electronic structures according to the present invention;

FIG. 23 shows an electronic structure according to the present invention;

FIGS. 24 to 27 show photovoltaic cells according to the present invention;

FIGS. 28A to 28H illustrate an embodiment of a photovoltaic module according to an embodiment of the present invention;

FIGS. 29A to 29G illustrate another embodiment of a photovoltaic module according to an embodiment of the present invention; and

FIGS. 30A to 30C illustrate a third embodiment of a photovoltaic module according to an embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 2 illustrates an embodiment of the method according to the present invention.

On a lower plate 10 is placed a bed of semiconductor powders 15, for example, silicon powders. An upper plate 20 covers powders 15. The assembly is placed in a processing enclosure and semiconductor powder layer 15 is compacted by application of a pressure P. The compaction may be performed by cold pressing, that is, at room temperature, or by hot pressing, at a temperature T, for example ranging between 950 and 1,300° C.

According to the present invention, the sintering is performed at least partially in liquid phase, that is, before or after the compression, a thermal processing such that part at least of the powders is melted, is applied. This is symbolized by letter F in FIG. 2. In the present invention, terms “liquid phase” and “melting” must be understood in a broad sense. As will be seen hereafter, “liquid phase” may also designate a viscous phase corresponding to an overmelted liquid, term “melting” then designating the “overmelting”.

The partial melting may be performed in selective fashion, for example, according to the area in the material, to the nature of the powders, or according to the used heating means.

In the areas sintered in liquid phase, the porosity is substantially zero (in practice, lower than 0.2%). Also, the melting causes an increase in the grain size, which is desirable, the obstacle to the displacement of the carriers created by the grain boundaries being then decreased.

Although this is possible, it is not necessary for the entire material to be sintered in liquid phase. Indeed, in its research, the inventor has found that it is not required for the features of a material intended to form a photocell to be homogenous throughout the entire material.

For example, in a photovoltaic cell, the so-called “absorbing” portion, that is, the area intended to turn the received photons into electron-hole pairs, must have a microstructure of very high quality, that is, a porosity as close as possible to zero and the largest possible grain size. The portion forming the junction (or collection area), intended to collect the carriers, must also exhibit this type of features.

However, other areas in the material do not need a high-quality microstructure and may exhibit with no disadvantage a poor porosity. Such areas for example are the heavily-doped N-type or P-type conductive areas used as a contact with the N and P areas of the junction. It is enough for these areas to exhibit a sufficient conductivity, and a porosity as high as 40 or 50% can be sufficient.

Accordingly, according to the present invention, the thermal processing may be carried out to selectively cause a melting only in the areas where a high-quality microstructure is desired.

A few examples of obtained materials will be given hereafter.

A number of trials have been carried out with pressures ranging between 10 MPa and 30 MPa (100 and 300 bars). The temperatures have ranged between 950° C. and 1,350° C. The used powders have been either pure silicon powders, or silicon powders mixed with powders of other elements from column IV of the Mendeleiev table, such as germanium, or silicon powders mixed with powders of non-semiconductor materials, such as silica SiO2. The granulometry of the used powders has ranged between 20 nanometers and 700 micrometers. The obtained results are spectacular. The objects of the present invention have been achieved and materials usable in the photovoltaic field have been obtained.

It should be noted that, according to the present invention, it is possible to easily control the morphology of the surface of the obtained material. Indeed, especially when the partial melting step occurs during the compression, the surface of the material faithfully reproduces the surface of plates 10 and 20. With planar and smooth plates, the surface, analyzed by electronic microscopy, appears as an even plane with a very low roughness.

It should also be noted that an advantage of performing a hot pressing of the powders, rather than a cold pressing, is that this provides a material exhibiting a low general porosity within a relatively short time, which results in a time, power, and cost saving.

It should also be noted that the liquid phase into which the material passes at least partially may be of very short time, for example, shorter than one minute.

For example, in a practical example, powders of a 20-nanometer size, sintered for half an hour by hot pressing under a 120-bar (12 MPa) pressure at a 1,325° C. temperature, provide a material with a porosity close to 4%. A thermal processing by laser beam causing a surface melting of the material will enable decreasing the porosity of the surface layer of the material down to practically zero.

It should be noted that the partial melting step is not necessarily distinct from the actual sintering step. The partial melting step may be carried out simultaneously to the compression.

Examples of implementation of the method according to the present invention will now be given.

The lower and upper plates are mechanical plates, sufficiently strong to enable the compression. They must be compatible with the nature of the used semiconductor powders to avoid introducing impurities. For example, the plates may be made of graphite or silicon carbide.

The powders of layer 15 for example are powders of pure silicon or silicon enriched in elements from column IV of the Mendeleiev table, such as carbide, germanium, tin, or their alloys. Powders of other semiconductors may also be used, and germanium, gallium arsenide AsGa, etc. materials may be formed by sintering.

The used powders may be of nanometric, micrometric, or even millimetric size. Preferably, the size of the powders is smaller than the thickness of the material which is desired to be obtained. However, it may also be slightly greater, the powders being crushed during the sintering. A mixture of powders of various granulometries may also be performed to form powder bed 15, especially to conveniently and efficiently control the general porosity or that of areas of the obtained material.

The used powders may originate from residues of the sawing of single- or polycrystal semiconductor ingots. Very thin powders resulting from byproducts of the decomposition reactors of the silicon composites, such as silane or trichlorosilane gases, may also be used. Such powders, typically on the order of 20 nanometers, currently have no industrial use. They are very inexpensive and their use makes the method according to the present invention even more economical.

Powder bed 15 may be formed in various manners. For example, one or several powder piles may be placed in various locations of plate 10 and the desired thickness may be equalized by means of a scraper. Powder bed 15 may also be formed by aerosol. In this case, a gas containing floating particles is sent to the processing enclosure. The particles deposit on plate 10 and form powder bed 15. Also, it is possible to use masks to place the powders at specific locations of layer 15.

It should be noted that the conditions of implementation of the method (pressure, thermal processing, powder nature and granulometry, processing time) enable controlling the features of the obtained materials and adjusting them in desired fashion.

A way to obtain the liquid phase (possibly, the viscous phase) is to use of mixture of powders such that part of the components melts (possibly, is made viscous) during the thermal processing which occurs, as it should be reminded, either during the compression step, or after.

For example, a homogenous mixture of germanium and silicon may be formed and brought to a temperature ranging between 937 and 1,410° C. The germanium melts (melting temperature 937° C.), but not the silicon (melting temperature 1410° C.). By melting, the germanium eases the transportation of silicon atoms from one silicon grain to another, as they aggregate. Further, the germanium spreads into the pores and clogs them, which results in the desired decrease in porosity. The same result may be obtained with a mixture of silicon and tin.

A sintering in liquid phase can thus be obtained by mixing powders of various materials, such as glass powders or ceramic materials, with the silicon powders. For example, the silica powders become soft and pasty from approximately 1100° C. and may also be used as a melting agent to sinter the silicon powders. It should be noted that, in this case, it is not properly speaking a liquid phase, and that this term rather designates a viscous phase, resulting from the passing of a component to the overmelted liquid state.

Generally, the liquid phase may be partially or totally evacuated during or after the sintering, for example by an anneal at high temperature, for example greater than 1,200° C. in the case of germanium. The liquid phase evacuation may also be favored by pumping at a pressure lower than the partial pressure of the considered component.

According to the present invention, the mixture of silicon and melting agent powders needs not be homogenous. For example, in a photocell where absorbing portion and junction are on a same surface, the melted portion of the powders only needs involving the surface portion of the mixture. This can be obtained by performing a surface heating by laser beam. This may also be obtained by forming a layer 15 in two sub-layers, a lower sub-layer with silicon powders and an upper sub-layer with a mixture of powders of silicon and melting agent, germanium for example, only the melting agent melting during the sintering. The obtained material is a material comprising a surface area exhibiting a high-quality structure.

The liquid phase may also be obtained by selectively melting powders exhibiting a specific doping type. Thus, for example, in a mixture of doped silicon and pure silicon powders, the doped powders may selectively be melted by induction, since their conductivity is higher than that of silicon.

Of course, in the method according to the present invention, several compression steps and/or several thermal processing steps may take place. The pressure and/or the temperature may vary along the implementation of the method according to the present invention. For example, the pressure may be exerted for a time shorter than the thermal processing. Also, the pressure may be applied intermittently during the thermal processing. Also, the thermal processing may comprise several steps, only one or several of which cause the melting.

It should also be noted that a stacking of several mechanical plates imprisoning several beds of semiconductor powders may be formed, to manufacture a great number of materials at the same time.

FIG. 3 shows a material 25 obtained by the method of FIG. 2. Material 25 appears in the form of a thin wafer, of a thickness typically ranging between 100 and 1000 μm. If need be, greater thicknesses, 2000 μm, for example, or lower thicknesses, such as 50 μm, may be provided. Material 25 is mechanically strong, of adapted porosity and its surface state is optimal. The dimensions of material 25 may be quite large.

FIG. 4 shows a structure 26 according to the present invention. Structure 26 comprises a mechanical support 27, such as an insulating or conductive ceramic, graphite, glass, a metal, or an alloy, on which is fixed a semiconductor material 28. Structure 26 is very robust and may be obtained in several manners. For example, material 25 of FIG. 3 may first be formed and fixed in any manner, for example, by gluing, to support 27. To form support 27, one of the two plates 10 or 20 of a nature such that the semiconductor material adheres thereto during the sintering of the powders of layer 15 may also advantageously be used. Such a plate is for example formed of silicon carbide SiC, silicon nitride Si3N4, silica glasses enriched or not with boron, phosphorus, nitrogen, etc. Structure 26 is thus directly obtained by the method of FIG. 2. Structure 26 may have any thickness. Support 27 may have a rather low thickness, for example, from one to a few millimeters, or rather high, for example, from one to a few centimeters. Structure 26 will be for example preferred in the case of semiconductor materials 28 of small thickness, for example, 50 micrometers, or when it is desired to form semiconductor wafers of very large dimension.

Material 25 and structure 26, very inexpensive, may be used as a base to form photovoltaic cells, by application of conventional doping, metallization, etc. methods.

However, the photovoltaic field is not the only possible application of material 25 or of structure 26.

For example, material 25 or material 28 of structure 26 may be used as a support for semiconductor layers deposited afterwards, which then are the active layers, materials 25 and 28 only being used as a support. This application is particularly advantageous. Indeed, materials 25 and 28 are compatible with the deposited layers, and in particular have the same expansion coefficient. In the deposition of the active layers, for example, in vapor phase, the high temperature then poses no problem of expansion difference between the deposited layers and the plate.

For example, material 25 or structure 26 may form wafers used for components for CCD cameras or flat screens, where such components may comprise transistors in thin layers.

A few possibilities provided by the method according to the present invention, relating to the texturation of the materials, their doping, and the forming of “composite” semiconductor materials, will now be described.

FIG. 5a illustrates a method according to the present invention in which a layer of semiconductor powders 30 is placed between a lower plate 32 of planar surface and an upper plate 34 having its lower surface exhibiting indentations 35. Indentations 35 may have a size on the order of one fifth of the thickness of layer 30. In the compression step(s), the lower surface of plate 34 prints the pattern of indentations 35 in layer 30. The material obtained by sintering of layer 30 faithfully keeps, at its surface, the pattern transmitted by plate 34. The texture of the material surface thus is perfectly controlled and it may for example be adapted to a better absorption of light. It goes without saying that it is preferable to carry out, in this case, the thermal processing leading to the partial melting during the compression step, to optimally keep the pattern transferred by the plate. Of course, the partial melting may also occur after, if the pattern modification due to the melting does not adversely affect the desired features.

FIG. 5b illustrates another example of a texture that may be obtained at the surface of a material according to the present invention. A lower plate 40 exhibits parallel parallelepipedal ribs 42. A bed of semiconductor powders 44 is placed on plate 40 and topped with an upper plate 46 of planar surface. After implementation of the method according to the present invention, the obtained material exhibits at its surface parallel depressions corresponding to the ribs of plate 40. As will be seen hereafter, such depressions may be filled with another material.

Various ways of doping the material according to the present invention will now be described through a few examples, in relation with FIGS. 6, 7A to 7C.

First, in the method of the present invention, it is possible to use previously-doped powders of semiconductor materials. The sintering of such powders provides a readily-doped material.

The obtained doping may be homogenous, when powders of a specific doping type, N or P, are uniformly distributed between the compression plates. Separate areas exhibiting a doping of different type and concentration may also be formed within the material by adequately distributing more or less heavily doped N- or P-type powders.

As seen, in the case of a mixture of pure silicon and doped silicon powders, the liquid phase may be obtained by only melting the doped powders. It should be noted that this further provides the advantage of decreasing down to almost zero the porosity of the doped areas. It may also be provided to only melt some of the doped areas.

A doped material may also be obtained by sintering a bed of undoped semiconductor powders to which are mixed dopants or impurities in the form of powders, such as boron, phosphorus, antimony, arsenic, gallium, aluminum, etc. It should be noted that these components melt easily and that, in melting, they optimize the microstructure of the area where they are present.

A homogenous doping of the material may also be obtained by means of undoped powders and by flowing a gas carrying dopant elements in the implementation of the method according to the present invention. Indeed, at the beginning of the processing, the porosity of the powder bed is very high, for example, on the order of 50%. The porosity is said to be open, that is, there exists, within the powder bed or the material being formed, interconnected circulation channels emerging outside. If a dopant gas then flows, the dopant gas spreads throughout the entire material and dopes it uniformly. The partial melting step, which clogs the porosity channels, must only take place after the doping or in areas which do not involve it.

To form a PN junction, an N-type material may be formed by sintering of powders. It is locally melted, for example, at its surface. It is then doped with a P-type doping via porosities, for example, by a gas. The portions which have not melted are P-type doped, while the portions having melted, with no porosity, keep the N-type doping. A large PN junction can thus be formed.

FIG. 6 illustrates another way of doping the material during its forming. A lower plate 60 comprises a duct 62 emerging outside. Duct 62 further comprises openings 64 located at the upper surface of plate 60. A powder bed 65 is placed on plate 60 to form the semiconductor material. A plate 66 comprising ducts 68 and 70 emerging outside and at the lower surface of plate 66 is placed above. Ducts 68 each connect the outside of the plate to a specific opening of the lower surface of plate 66. Duct 70 connects the outside of plate 66 to several openings located on the lower surface of plate 66.

In the compression step, a dopant gas, for example, of type P, is sent into duct 62. This gas, due to the large number of open porosities existing at the beginning of the forming of the material, causes, in front of openings 64, the doping of areas 74 delimited in dotted lines. According to the gas sending conditions, the different doped areas 74 may join. The thermal processing step will have to be adapted to the desired result. Indeed, the open porosities close during the thermal processing step. According to the time of action of the gas in the process, it is possible to perform local dopings. Dopant gases are also sent into ducts 68 and 70 to respectively form doped areas 76 and 78. Since it is possible to separately modify the gas sending conditions into each of ducts 68 and duct 70, a size, a doping type and concentration may be obtained for each of areas 76 and 78. “Gas sending conditions” is especially used to designate the nature, the flow rate or the pressure, the action time of the gases, the time when they act, etc.

Another way of doping the material obtained according to the present invention will now be described in relation with FIGS. 7A to 7C.

FIG. 7A schematically shows a view partially in cross-section and in perspective of a P-type material 80 obtained by sintering of powders according to the method of the present invention. Material 80 exhibits depressions 82 and 84 which have been obtained by means of a plate exhibiting protruding elements of corresponding shape, of a type similar to those of plate 40 of FIG. 5b . The width of depressions 82 and 84 may be as small as 1 μm. The edges of depressions 82 and 84 are well delimited. Depression 82 is meander-shaped and depression 84 is rectilinear. Depressions 82 and 84 are then each filled with semiconductor powders exhibiting a doping of desired type and concentration.

In FIG. 7B, material 80 exhibits heavily-doped N-type areas 86 (N+) and a heavily-doped P-type area 88 (P+). These areas have been obtained by filling depression 82 with N-type powders, and depression 84 with P-type powders, then by sintering these powders. For this purpose, the material may simply be submitted to a thermal processing step.

FIG. 7C shows a top view of a semiconductor material 90 according to the present invention, in which heavily-doped N-type areas 92 and heavily-doped P-type areas 94 have been obtained according to the method described in relation with FIGS. 7A and 7B. Areas 92 and 94 are interdigited. The surface comprising areas 92 and 94 is intended to be the surface unexposed to light. This makes the forming of a collector comb such as comb 5 of FIG. 1 useless and correspondingly increases the lit surface of the photocell.

It should be noted that the materials comprising PN junctions described hereabove are components very close to the end product embodied by a photocell. The method according to the present invention enables further approximating the end product.

On the one hand, when the PN junction is across the thickness of the material, it is possible to place a bed of aluminum powders at the base of the semiconductor powder bed in the material manufacturing. The material obtained after sintering thus comprises the lower conductive layer, which no longer needs being deposited afterwards. A heavily-doped P-type area, such as area 3 c of FIG. 1, is naturally produced at the contact between the P-type material and the aluminum. A thin layer of heavily-doped P-type powders, for example, from one to a few micrometers, can thus be placed on the layer of aluminum powders on manufacturing of the material. The upper collector comb may also be formed on formation of the material, by placing adequate powders, such as aluminum powders, at the appropriate locations. Transparent conductive ceramic powders may also, for the transmission of current, be placed over the entire surface of the material exposed to light.

On the other hand, when the PN junction is at the surface, as in FIG. 7C, conductive powders may be deposited on the powders intended to form the doped areas (non-lit surface of the material) before their thermal processing. The obtained material thus comprises two interdigited conductive areas, which form particularly efficient collectors of the carriers created by photoelectric effect.

A material according to the present invention obtained by sintering of semiconductor powders of different nature will now be described. The used powders may belong to any element of column IV of the Mendeleiev table, and/or to their alloys.

FIG. 8 schematically shows a top view of a material 100 according to the present invention. Material 100 has been obtained, for example, by application of the method according to the present invention to a bed of powders comprising powders of tin Sn, germanium Ge, silicon Si, and carbon C. An area 102 formed of tin runs along edge 104 of material 100. Area 102 results from the sintering of tin powders placed along lateral edge 104. The uneven contour of area 102 can especially be explained by the fact that tin melts at temperatures used in the method and tends to spread into the open porosities of the material. Material 100 also comprises islets 106 of germanium Ge, resulting from the sintering of germanium powders. Similarly, the silicon powders create silicon islets 108 and the carbon powders which, in the shown example, have been deposited rather towards edge 112 of the material, create islets of carbon C.

Further, material 100 comprises islets 114 of SiGe alloy, islets 116 of SixGe, SiyC islets 118. The material may also comprise GexC and SixGeyC islets. Such alloys appear at the contact of the grains of different nature in the thermal processing, the various grains aggregating by sintering. If this is desired, the forming of these alloys may be limited by placing the powders of different nature so that they avoid mixing too much. Powders of various alloys may also be arranged in the bed of powders to be sintered, to increase the proportion of the alloys. Further, the used powders or the obtained materials may be doped as described hereabove.

It should be noted that with conventional methods for manufacturing semiconductor materials, such as methods using melts, only homogenous alloys may be obtained and a “composite” material such as material 100 cannot be obtained.

Material 100 is particularly advantageous in photovoltaic applications.

Indeed, the wavelength of the radiations absorbed by a semiconductor element depends on the value of the energy gap of this element. Thus, silicon, having an energy gap of 1.1 eV, is naturally optimized for visible light. Infrared radiations are practically not absorbed by silicon. Ultraviolet radiations, as for them, are rapidly absorbed by silicon, but the excess energy represented by the difference between the energy of the radiation and the value of the energy gap is lost. Germanium, having a 0.7-eV energy gap, is particularly well adapted to absorb infrared light. An alloy of SixGe type has an energy gap ranging between the energy gap of silicon and that of germanium. An SixC-type alloy has a much greater energy gap than that of silicon. An alloy of this type responds particularly well to blue and ultraviolet radiations.

As a result, material 100 has a locally variable energy gap. This is an extremely significant advantage, since the radiations can be used at best in a photovoltaic application. For example, material 100 may practically respond to the entire solar spectrum, which is not the case for a conventional silicon photocell.

FIG. 9 schematically shows a bed of powders 120 intended for the forming of a material according to the present invention. Powder bed 120 comprises a lower layer 122 of tin powders, followed by a layer 124 of germanium powders, followed by a layer 126 of silicon powders, the assembly being topped with a layer 128 of powders of a carbon and silicon alloy SixC. The layers of powders 122, 124, 126, and 128 are arranged by increasing energy gap order.

After sintering, the obtained semiconductor material thus comprises several superposed layers of materials of different energy gaps. In a photovoltaic application, the surface of the material comprising the layer with the larger energy gap, SixC, is exposed to light. Alloy layer SixC absorbs the ultraviolet radiation and around and lets through visible and infrared radiations. The silicon layer absorbs the visible light and is practically transparent to infrared radiations, which are absorbed by the germanium layer. Various alloys created during the sintering help the absorption of the radiation. The tin layer, buried, is mainly used to collect the carriers created by the photovoltaic effect. As previously, a PN junction may be formed by an appropriate doping.

As compared with the material of FIG. 8, the material obtained by the powder bed of FIG. 9 is advantageous in that the radiations successively cross layers of decreasing energy gaps. This enables more complete absorption of the radiation.

Of course, the present invention is not limited to the described examples and any variation, modification, or the like within the abilities of those skilled in the art belongs to the field of the present invention.

In particular, the plates used to compress the powder bed are not necessarily planar and may have any shape.

FIG. 10 thus shows a tile-shaped semiconductor material 130 that may integrate to the structure of a roof. Material 130, which will be called tile hereafter, comprises a non-planar end 131 enabling covering the next tile 130′ and connecting thereto. Tile 130 is obtained by sintering of a bed of semiconductor powders by means of plates of corresponding shape. The powder bed has been formed to successively create a thin heavily-doped N-type layer 132 (N+), an N-type doped layer 134, followed by a P-type doped layer 136. At the end opposite to end 131 is a heavily-doped P-type area of small extension 138 (P+). Tile 130 is connected to tile 130′ by any conductive attachment means 140, such as a welding or a flexible wire, connecting the N+ layer of a tile to the P+ area of the next tile. The photocells formed by tiles 130 and 130′ are thus series-connected. Various other ways of grouping a set of tiles, in series and/or in parallel, provide the desired features of an installation.

It should be noted that, for the melting step, any appropriate means, such as resistive furnaces, lamp furnaces, solar furnaces, etc. may be used, the power being transferred by conduction, convection, radiation, etc.

It should also be noted that any structure or component comprising or formed of one or several materials according to the present invention belongs to the field of the present invention.

It should also be noted that the materials according to the present invention are not limited to the materials obtained by the method according to the present invention. For example, any semiconductor material comprising grains and/or aggregates exhibiting different energy gaps belongs to the field of the present invention, whatever its obtaining mode.

Some further embodiments or aspects of the present invention will now be described in relation to FIGS. 11 and 12.

According to the following aspect of the present invention, the materials or wafers produced by the method of the present invention can be purified during their production steps. This aspect of the present invention is particularly useful if the powders used to form the sintered material are not very pure.

The inventor has found that it was possible to purify a porous semiconductor material using a gas flow through the material. The inventor explains the good results in purification by two factors. First, the gas flows through the porosity channels of the material, and reaches great parts of the inner volume of the material. Second, due to diffusion, impurities inside the material reach the porosity channels and can be evacuated out of the material by the gas flow. As this will be seen later, the gas which is used for the purification can be a non reactive gas, or a gas which reacts with impurities of the material. In the latter case, impurities can form, with the gas or other atoms or molecules present or formed in the material, volatile components which are carried out of the material by the gas flow. The purification of the material can be performed during the production of the material, that is, during the sintering of the powders, or after the production of the material. The materials purified according to the present invention can be used in the photovoltaic, electronic, or microelectronic field.

The purification of the material allows the use of powders which are not very pure. For example, the powders can derive from parts of single-crystal or polycrystalline silicon ingots which are not sufficiently pure, like head, tail and edges of the ingots. The source material can also be damaged wafers or wafers with defects, at any stage of the fabrication of photovoltaic cells, electronic components or integrated circuits. If the source material is already doped, the purification according to the present invention allows also the production of purified material. Silicon used in metallurgy can also be used in the present invention. For example, silicon including one or some percent of iron can be purified by the present invention.

The source material can of course comprise all or several of the elements mentioned above. If the source material is not already present in the form of powders, the method of the present invention provides a grinding step for providing powders from the source material. The powders can be of various sizes, but a size less than 10 micrometers can be preferred.

The production of purified wafers according to the present invention will now be described in relation with FIGS. 11 and 12.

FIG. 11 shows in cross-section an assembly 150 comprising a lower plate 10′, a bed of semiconductor powders 15′, for example silicon powders, and an upper plate 20′ which covers powders 15′. The assembly 150 is similar to the assembly shown in FIG. 2, except that lower plate 10′ and upper plate 20′ are made of a porous material, for example a porous ceramic or graphite, allowing the passage of a gas.

The powders of bed 15′, like the powders 15 of FIG. 2, for example are powders of pure silicon or silicon enriched in elements from column IV of the Mendeleiev table, such as carbon, germanium, tin, or their alloys. Powders of other semiconductors may also be used, and germanium, gallium arsenide AsGa, etc. materials may be formed by sintering.

The powders may be of nanometric, micrometric, or even millimetric size. Preferably, the size of the powders is smaller than the thickness of the material which is desired to be obtained. However, it may also be slightly greater, the powders being crushed during sintering. A mixture of powders of various granulometries may also be performed to form powder bed 15′, especially to conveniently and efficiently control the general porosity or that of areas of the obtained material. Powder bed 15′ may be formed like powder bed 15 of FIG. 2.

FIG. 12 shows a reactor 190 allowing the production and the purification of wafers according to the present invention.

In FIG. 12, reactor 190 comprises a matrix 192 forming a chamber 194. A lower plate 196 and an upper plate 196′ close chamber 194. Plates 196 and 196′ are made of a porous material. Matrix 192 can also be made of a porous material, but it is not necessary. Matrix 192 and plates 196, 196′ are disposed in an enclosure 200 comprising at least an input opening 202 for inputting a gas G and a gas output opening 204.

Several assemblies like assembly 150 of FIG. 11 are arranged in chamber 194, so as to produce a lot of wafers simultaneously.

To produce the wafer, a pressure P is exerted between plates 196 and 196′. A pressure P ensures a compacting of the silicon powders 15′, plates 10′ and 20′ compressing the powders.

Reactor chamber 194 is then submitted to a thermal processing at a temperature T, in order to provide a sintering of the wafers. The thermal processing can be applied, as already explained, during or after the compacting of the powders. The pressure exerted in the compression step may vary within a wide range of values, for example, from 10 bars (1 megapascals) to 10,000 bars (1 gigapascal). The temperature used in the thermal processing step may also vary within a wide range of values. For example, it may be comprised between 800 and 1400° C. for silicon.

As already mentioned, the purification step can be performed during one of the formation steps of the material. Of course, the purification steps take place before the liquid phase occurs if a liquid phase is needed. If this was not the case, the liquid phase would close a lot of porosity channels, and the gas would be unable to flow through the material for purifying it.

Some of the possible operating modes will now be described.

For example, it is possible to perform a hot pressing step of the powders while a purification due to gas flow takes place.

Also, a hot pressing step can be performed in order to form the material. Then, the purification step can take place, in the same enclosure as the enclosure used for the hot pressing step, or in a separate enclosure.

Also, a cold pressing step can be first performed. Then, the thermal processing and the purification step can be performed together, or separately.

In all the cases, when needed, the steps producing a liquid phase in the material take place after purification.

Characteristics of the purification step or steps will now be described.

Gas enters enclosure 200 via opening 202. Then, the gas enters chamber 194 through porous plates 196, 196′, and matrix 192 if matrix 192 is porous. The gas passes then through the assemblies 150 of chamber 194, via plate 10′, the porosity channels of the material which is being formed, and plate 20′.

Instead of being made of porous material, one or more elements among plates 196, 196′, matrix 192, plate 10′, and plate 20′ can be made of a non porous material pierced with small traversing openings allowing the gas to pass. For example, these opening can be small conducts with a diameter of 0.1 to 1 millimeter.

The purification step, using a gas flow, can be made at various times of the formation of the wafers. For example, it can be performed at the first stages of powder compaction. It can be performed also at one of the last stages of the sintering of the material. It is just necessary that the porosity of the material remains an open porosity, that is that the porosity channels within the material are interconnected and lead to the outside the material.

The material is more rapidly purified if the temperature is high, because impurities have a better mobility and can reach more easily the porosity channels. For example the temperature is comprised between 800° C. and the melting temperature of the material. It is advantageous to purify the material during the or one of the thermal processing steps of the sintering process.

Various durations can be used for the purification step. For example, the duration of the purification step will be of about half an hour to one hour after chamber 194 has reached the desired temperature, the duration of which can also be in the order of about half an hour to one hour. The duration of the purification process depends on various factors. For example, if powders have a small size, the porosity channels are close one to the other and impurities reach quickly the porosity channels, whereby the material is purified faster.

Various gas pressures can be used, and the gas pressure can change during the purification step.

If the gas pressure is more than one atmosphere, a gas flow occurs naturally between opening 202 and opening 204.

If the gas pressure is less than one atmosphere, the pressure in chamber 194 is a low pressure, for example ranging from 1 to 10 hectopascals. In this case, the gas is pumped at opening 204, for creating the gas flow and evacuating the gas at the outside.

Various sorts of gas can be used.

For example, the gas can be a non reactive gas, like argon. When a non reactive gas flows through the porosity channels of the material, impurities which are not or only little linked to the walls of the porosity channels can be detached and carried out of the material by the gas flow. Further, due to diffusion, impurities inside the material but not present in a porosity channel can reach a porosity channel and be evacuated.

Preferably, the gas is at least partly a reactive gas which chemically reacts with a particular type of impurities to provide volatile components at the temperatures which are utilised. These volatile components are evacuated outside the material by the gas flow. The gas can also be a mixture of a carrier gas, like argon, and at least one reactive gas.

The type of the reactive gas depends on the type of impurities to be eliminated.

A type of very polluting impurities of silicon, which are very difficult to eliminate at low cost, are the metallic impurities. These metallic impurities comprise titan Ti, tungsten W, molybdenum Mo, iron Fe, chromos Cr or copper Cu. The inventor has found that a flow of a gas containing chlorine, like chlorine Cl2 or hydrochloric gas HCl, in the porosity channels of the material, reacts with the atoms of titan present in the material to form a volatile component, TiCl4, carried away and evacuated by the gas flow. Atoms of titan not present in or at the surface of porosity channels can reach a porosity channel due to diffusion, and are then likely to react with the gas. As a result, the purification process of the present invention provides a material without titan, as all the inner volume of the material can be reached by the porosity channels. A gas containing chlorine can eliminate other impurities than titan, as the majority of metals, like iron or copper, reacts also with chlorine. A gas containing fluorine like CF4, SF6 or CCl12F2, or containing bromine like HBr can also be used. To eliminate tungsten, a gas containing fluorine will be used, as tungsten forms with fluorine a volatile component, WF6, carried out of the material by the gas flow. Molybdenum reacts with CF4 to form a volatile component, MoF6, which can be evacuated.

Another type of impurities comprises non metallic impurities like oxygen and carbon. Oxygen is mostly present as the oxide which is naturally present at the surface of the powder particles. A gas containing hydrogen reduces oxides, which are evacuated outside the material. The gas which is used can be the hydrogen gas H2, or a gas containing hydrogen, like the hydrochloric gas HCl or the ammoniac gas NH3. Carbon is also evacuated by gases containing hydrogen because carbon provides volatile hydrocarbons, like methane CH4, depending on the conditions in chamber 94, for example a temperature of about 1000° C. with a mixture of gases containing argon and about 10% of hydrogen H2.

Regarding alkaline-earth impurities, like sodium, calcium, magnesium or manganese, the inventor has noticed that, at the used temperatures, these impurities are greatly evacuated using a mere pumping, without injecting a gas. The injection of a non reactive gas helps in eliminating these impurities. Further, if a gas containing chlorine is used for eliminating other impurities, chlorine also eliminates alkaline-earth impurities, like sodium and calcium.

Doping elements can be also suppressed by the method of the present invention. Indeed, phosphorus, boron, arsenide, gallium, aluminum can provide volatile complexes with hydrogen, chlorine and/or carbon. For example, an atom of boron can be combined with an atom of hydrogen and a SiO particle to form an atom of silicon and a molecule of HBO, which can be evacuated. Boron can also be evacuated using water-vapor. Some doping elements can also be evacuated by the gas flow merely when temperature is high.

It should be noted that the gas which is used can be a mixture of gases, if the gases are compatible at the used temperatures. For example, it is possible to use a gas mixture comprising 95% of argon Ar, 4% of hydrogen H2 and 1% of chlorine Cl2. If incompatible gases should be used, they will be used the one after the other.

It should also be noted that the present invention allows a selective cleaning of impurities, depending on the conditions and on the nature of the gas. Thus, silicon powder with for example 10 ppm of boron and 10 ppm of phosphorus can be purified from one of the doping elements to become a doped material of the N or P type. The inventor has remarked that phosphorus is easily eliminated at temperatures above 1200° C. due to its vaporization. To eliminate boron, a part of water-vapor in argon at a temperature ranging between about 700 to 900° C. can be used to produce the volatile molecule HBO.

Further, pumping can be advantageous. Indeed, a component to be eliminated may have a saturating vapor pressure and be in equilibrium with its vapor in a porosity channel of the material. Continuously pumping in this case decreases the vapor pressure and the component to be eliminated produces more vapor, which may accelerate the speed of the process for eliminating this component.

Of course, as already mentioned, the present invention is likely to have various alterations and modifications which will occur to those skilled in the art.

In particular, it should be noted that every step of the purification and/or formation of the material can be split into a plurality of steps.

Also, the method of the present invention may provide other materials than semiconductor materials, and the purification steps of the present invention may be applied to any porous material.

Also, when the present invention is applied to elaborate materials for the photovoltaic, electronic or microelectronic field, the powders which are used are not necessarily powders of a unique semiconductor. For example, the powders may be powders of silicon mixed with powders of any other element of column IV of the Mendelieïev table, like Germanium Ge. The powders may also be semiconductor powders mixed to powders of non semiconductor materials, like silica SiO2.

Some further embodiments or aspects of the present invention will now be described in relation to FIGS. 13 to 16.

Structure 301 of FIG. 13 comprises a support layer 302 and an upper layer 304 lying on support 302.

Support 302 is formed of a silicon wafer obtained by sintering silicon powders. This sintered silicon wafer is obtained by compressing and thermally processing silicon powders. Examples for providing the sintered silicon wafer are described above.

Support 302 preferably comprises relatively small silicon grains and is porous. The thickness of support 302 can vary in a broad range of values. Preferably, the thickness of support 302 is greater than 50 micrometers, for example comprised between 200 and 500 micrometers. It should be noted that, due to the low cost of sintered silicon wafers, support 302 can be relatively thick, for example one to several millimeters, which provides robust wafers without substantially increasing the costs. This provides a great advantage in the photovoltaic field. Indeed, in the prior art, wafers are very thin for costs reasons, and a lot of wafers brake during the fabrication of photovoltaic cells.

Layer 304 is a single-crystal silicon layer. The thickness of layer 304 can be in a broad range of values. The thickness of layer 304 is typically in the order of 30 to 50 micrometers if structure 301 is intended to be used in the photovoltaic field, and typically in the order of one micrometer in others applications, such as in microelectronics. Layer 304 is intended to be the active layer of structure 301. Layer 304 can be obtained by gluing after removal, as will be now described in relation to FIGS. 14A to 14D.

Reference 310 in FIG. 14A represents a thick single-crystal silicon plate. Plate 310 has for example a thickness of one millimeter and is intended to provide layer 304 of structure 301. There is a default zone 314 near the upper surface 312 of plate 310. Default zone 314 can for example be provided by a chemical treatment which renders surface 312 porous while keeping the single-crystal structure of plate 310.

Then, as shown in FIG. 14B, an epitaxial layer 316 of single-crystal silicon is provided. Layer 316 is intended to form active layer 304 of structure 301 and its thickness depends on the desired application.

In FIG. 14C, epitaxial layer 316 is removed from plate 310. For example, a plate 318 of glass or plastic is glued on layer 316 and a force A is applied on plate 318 in a direction which may or may not be perpendicular to surface 312. Due to default zone 314, layer 316 is separated easily from plate 310. Other techniques, such as ultrasonic or pressurized water jet removal can be used to remove layer 316.

In FIG. 14D, the combination formed by layer 316 and plate 318 is placed onto support 302 and a pressure B can be applied to make gluing easier, the gluing being performed by molecular gluing. Upper surface of support 302 as well as lower surface of layer 316 may have been processed prior to gluing, for example using etching or polishing, to make gluing easier. If this is desired, a thermal processing with or without compression can be performed, so that glued surfaces have a better mechanical strength. Then, plate 318 is removed and the combination of support 302 and layer 316 forms structure 301 of FIG. 13.

Structure 301 is thus formed of a sintered silicon wafer 302 and an active single-crystal silicon layer 304. Various dopings and/or connection elements can then be implemented in or on active layer 304 to provide a desired device, such as one or several integrated circuits, one or several electronic components, one or several photovoltaic cells, etc.

The fact that the support of the active layer is made of sintered silicon can have significant advantages.

The support and the active layer being both of silicon, they have similar physical and chemical properties. A consequence is that the various fabrication steps of the desired device can be performed without the occurrence of particular problems, such as problems due to a bad temperature behavior of the support, problems due to thermal expansion differences between support and active layer, etc.

Further, the surface of the sintered silicon wafer is naturally relatively rough and allows if necessary a later removal of the active layer. This allows for example, once the desired device has been fabricated, to remove the active layer and to transfer it on another support which, due to its physical and/or chemical properties, would not have permitted the desired device to be fabricated.

It should be noted too that, when sintering the silicon powders to provide support 302, doping elements can be mixed with the powders in order to dope the wafer. For example, a high doping with boron renders support 302 conductive, which allows a rear electrode in structure 301 to be provided.

Further, the control of the sintering of silicon powders allows a sintered wafer having a determined porosity, in which the porosity channels are interconnected and reach the outside. The porosity channels can be used to introduce elements inside the support wafer. For example, if the wafer has not yet been doped, doping elements can be introduced deeply into the wafer structure. The porosity channels can also be filled with a conductive material, for example using an aluminum paste which is spread on the underside of layer 302 and melted. The porosity channels can also be used to establish a connection between the bottom of the active layer and the outside, without the need of providing a connection on the upper surface of the active layer. This can be a significant advantage if the desired device is a photovoltaic cell, because the upper surface of the active layer, which is exposed to the sun, is larger and the conversion of the cell is increased.

Among other advantages provided by a sintered silicon support, it should be noted that the support wafer can have any form and can be of a small or large size, depending on what is needed. Also, the desired form and size of the wafer can be obtained directly when fabricating the wafer, for example by placing the powders in an appropriate mould. Also, the wafer is not necessarily flat. The surface of the silicon wafer can be curved and have for example the form of a tile adapted to the roof of an existing building. This is an advantage for photovoltaic cells.

FIG. 15 shows another structure according to an embodiment of the present invention.

In FIG. 15, a structure 330 comprises a lower layer 332 forming a support, an upper layer 334 and an intermediate layer 336. The lower layer 332 is formed of a sintered silicon layer, like support 302 of FIG. 13 and its thickness is similar. Intermediate layer 336 is a thin layer forming a diffusion barrier. Layer 336 can for example be a layer of silicon oxide (silica) SiO2, of silicon nitride Si3N4, or of silicon carbide SiC. The thickness of layer 336 is very thin, typically less than 10 nanometers. Upper layer 334 is a single-crystal silicon layer, which can have been moved onto layer 336 using the method of FIGS. 14A-14D. Layer 334 is intended to be an active layer. A typical thickness of layer 334 is for example in the order of one or a few micrometers for microelectronic applications and from 30 to 50 micrometers for photovoltaic applications.

The thin layer 336 provides advantages because layer 336 acts as a diffusion barrier and can block impurities contained in lower layer 332. This allows the use of impure silicon powders to form support wafer 332.

Structure 330 also has the advantages of structure 301 of FIG. 13 (possibility of large wafers, non-planar wafers, advantages linked to a silicon support, etc). It is also possible to use the porosity channels of the support wafer to introduce dopants or a conductive material providing an electric contact with the lower part of the active layer. Indeed, although formed of a material that is usually considered as an insulating material (silica, silicon nitride, silicon carbide), layer 336 is very thin and conduction mechanisms such as tunnel injection or injection of charges through defects enable layer 336 to conduct electrical current. It should further be noted that the presence of the thin layer 336 can allow a better molecular gluing of the active layer.

FIG. 16 shows another structure according to an embodiment of the present invention.

In FIG. 16, a structure 340 comprises a lower layer 342 forming a support, an upper layer 344 and an intermediate layer 346. The lower layer 342 is formed by a sintered silicon wafer. Upper layer 344 is a single-crystal silicon layer. Intermediate layer 346 is a thick insulating layer. Insulating layer 346 can be made of silica SiO2, silicon nitride Si3N4, or silicon carbide SiC, etc.

The thickness of the lower layer 342 can be in the same order as lower layer 332 of FIG. 15, typically greater than 50 micrometers. It can also be thicker, for example a few millimeters, because its fabrication cost is low. The thickness of upper active layer 344 depends on the use of structure 340. Thus, a thickness of 30 to 50 micrometers for layer 344 is adequate for a use in the photovoltaic field. The thickness of insulating layer 346, which is not critical, is typically in the order of 100 nanometers to a few micrometers. It should be noted that a thickness greater than 10 nanometers is sufficient to render layer 346 insulating.

Insulating layer 346 provides a very efficient barrier to impurities. Thus, very impure silicon powders, for example metallurgical silicon powders, can be used to make support 342, without contamination of the active layer by impurities of the support.

It should be noted that, as support 342 is electrically insulated from active layer 344, structure 340 can be used as a so-called “SOI” (Silicon On Insulator) structure for all the applications where structures of the SOI type can be used. An advantage of structure 340 is that it is much less expensive than conventional SOI structures, in which the active layer is on a single-crystal silicon substrate.

Generally, as support 342 is electrically insulated from active layer 344, all the electrical contacts should be provided on the front face of the device, that is on the upper surface of the active layer. However, it should be noted that it is also possible to provide electrical contacts on the rear face, as in the case of structure 330 of FIG. 15.

In that case, a plurality of holes 348, shown by dotted lines in FIG. 16, can be provided. Holes 348 are for example created with a laser beam from the rear of the structure and stopped when they have passed through insulating layer 346. Holes 348 are then metallized to provide electrical contacts. The diameter of holes 348 can be in the order of one to a few tens of micrometers.

Of course, the present invention is not limited to the examples described in relation to FIGS. 13-16, and any variation, modification, or the like will be within the abilities of those skilled in the art.

In particular, the thicknesses of the described layers are just indicative and can be modified to a great extent. For example, the thickness of the single-crystal silicon layer may range from less than 1 μm to several hundred μm such as 500 or 600 μm.

Also, the sizes or forms of the wafers have not been described in detail and can be of various types. For example, to make photovoltaic cells, the wafers can be squares having edges of 15 cm.

Also, layers 336 and 346, which are shown between support layer and active layer in the figures, can completely surround the support layer on all sides, in which case the man skilled in the art will know to provide the necessary arrangements if electrical contacts have to be present at the rear of the structure.

Also, holes 348 of FIG. 16 can also be present in support wafer 302 of FIG. 13 or in support wafer 332 of FIG. 15. These holes will be in any case used if it is desired to have access to the active layer from the rear face of the structure and if the support wafer has been formed without open porosity, that is if the porosity channels are not interconnected and do not open to the outside.

The present invention can be applied in the photovoltaic field, in all the fields in which a structure of the SOI type can be used, as well as in optics, optoelectronics, electronics, microelectronics, etc. For example, the present invention can be used for the fabrication of discrete electronic components, electronic chips, microprocessors, CPUs, electronic chip supports, in 3D integration, etc.

Some further embodiments or aspects of the present invention will now be described in relation to FIGS. 17 to 27.

For clarity, the same elements may have been designated with the same reference numerals in the different drawings and, further, as usual in patent applications, the various drawings are not to scale.

In FIG. 17, an enclosure 401 encloses a lower plunger 403 and an upper plunger 404. Silicon powders 406 have been placed between the lower and upper plungers. Enclosure 401 comprises a gas inlet opening 407 and a gas outlet opening 409.

A gas flow G is established between openings 407 and 409. Enclosure 401 is brought to a temperature T. A pressure P is applied between plungers 403 and 404.

Silicon powders 406 are sintered and transformed into a rigid sintered silicon wafer.

There may be a great variety of sintering conditions.

For example, the size of powders 406 is not critical. For example, the powder granulometry may range between 10 nanometers and 100 micrometers. A mixture of powders of different granulometry can be made, like nanometric powders and micrometric powders.

The quality of the powders is not critical either. As will be seen hereafter, solar grade or electronic grade silicon powders may be used. So-called metallurgical grade or MG powders or so-called upgraded metallurgical silicon or u-MG powders may also be used.

Temperature T may range between 1,000 and 1,400° C. Pressure P may range between 5 and 100 megapascals. Temperature T and pressure P may be applied jointly, during one or several hot compression steps, or successively, during one or several compression steps followed by a thermal processing. Temperature T and/or pressure P are not necessarily fixed during the sintering.

The pressure of gas G may for example vary between a few hectopascals and more or less 1,000 hectopascals. Gas G may be argon. Hydrogen may be added thereto to reduce the oxygen present in the powders, together with another gas, for example, a halogenated gas, to purify the powders. Various gases and operating modes for purifying a sintered wafer after it has been formed or during its forming have been described in the foregoing and can be used. For example, plungers 403 and 404 may be porous to let the gas flow through the porosity channels of the material which is being sintered. The purification can be performed during the first phases of sintering the material, for example when the wafer is compacted and preheated, before one or several hot pressing steps.

The gas flow may be sustained or not during the entire sintering. It should further be noted that the presence of a gas flow is not essential and that the sintered wafers may be manufactured with no gas flow. In such a case, enclosure 401 does not necessarily include openings 407 and 409. FIG. 17 is only a non limiting example for making a sintered wafer.

FIG. 18 shows a sintered silicon wafer 410, obtained after sintering.

Wafer 410 has a length L, a width I, and a thickness h. For example, square wafers having a side of 150-millimeter and having a thickness h ranging between 100 and 500 micrometers may be formed. Circular, diamond-shaped, or hexagonal wafers may also be formed, since the wafers may have any shape, however preferably tileable. Wafer 410 is not necessarily planar either, but may be adapted to a desired shape, for example to the shape of a roof tile. Wafer 410 is formed of small grains 412, symbolized by crosses in FIG. 18. Generally, the sintering does not increase the grain size much. For example, if powders with dimensions on the order of one micrometer are used, grains 412 will have a size that may range from 1 to 3 micrometers according to the sintering conditions.

Wafer 410 may be made in non-porous or porous form, with a porosity that can be controlled by the wafer manufacturing conditions.

Further, wafer 410 is generally N-type and/or P-type doped, types N+ and/or P+ being preferred. Types P+ and N+ should be understood as corresponding to dopant concentrations greater than 1018 atoms/cm3, for example, ranging between 1018 and 1021 atoms/cm3, and types P or N should be understood as corresponding to dopant concentrations smaller than or equal to 1018 atoms/cm3, for example ranging between 1015 and 1018 atoms/cm3. The doping may be performed during the sintering. For example, previously-doped powders may be used, or dopants may be mixed to the silicon powders or provided by gas G which flows in the porosity channels. In the case of porous wafers, the doping may also be performed after the sintering, that is, after the forming of wafer 410. For example, the dopants may be introduced by injecting a gas, a liquid or viscous product which penetrates into wafer 410 via the porosity channels. A paste containing dopants may also be applied on one or both surfaces of the wafer, to have the dopants penetrate by diffusion. The dopants may be added in one or several steps. The doping may be homogeneous, exhibit a gradient, or be local, that is, present in one or several different portions of the wafer.

FIG. 19 shows an example of a wafer 410 with a local doping.

In FIG. 19, wafer 410 has N+-type doped areas 415 alternating with P+-type doped areas 417. Areas 415 and areas 417 appear in the form of strips taking up the entire width I and the entire height h of wafer 410. For example, the width of areas 415 is on the order of 2 millimeters and the width of areas 17 is on the order of 1 millimeter. The doping of areas 415 and 417 is performed after the manufacturing of wafer 410, which here has been made in porous form. The dopings may for example be performed by injecting liquid or a viscous product into the wafer pores. Areas 415 and 417 can thus be formed by serigraphy, followed by an anneal step for diffusing the dopants.

Areas 418 are located between areas 415 and 417. Areas 418, for example, having a width on the order of one millimeter, may enclose an insulator, such as silica SiO2. The insulator may have been introduced by a method similar to that used for the doping, for example, by applying a paste containing silica on the corresponding portions of the wafer surfaces and by having said paste penetrate through the porosities.

The injection of an insulator into areas 418 is not compulsory. There will for example be no such injection if wafer 410 has been made from undoped or lightly-doped solar or electronic grade powders, since such powders, once sintered, have a much smaller resistivity than the N+ or P+ doped areas. However, the injection of an insulator into areas 418 is recommended if the powders used are MG or u-MG powders. Indeed, in this case, the metallurgic silicon risks being conductive and creating disturbing leakage currents.

Of course, FIG. 19 is an example of local doping only, and patterns other than strips may be designed for areas 415 and 417.

Once wafer 410 has been made and doped, a surface of wafer 410 is recrystallized, as will be described in relation with FIG. 20.

In FIG. 20, an enclosure 420 encloses a lower counter-plunger 423 and an upper counter-plunger 424. Wafer 410 is placed between the lower and upper counter-plungers. Counter-plungers 423 and 424 exert no particular pressure on wafer 410. Counter-plunger 423 is brought to a temperature T1 below the silicon melting point, that is, below 1,414° C. Counter-plunger 424 is brought to a temperature T2 greater than the silicon melting point. As a result, counter-plunger 424 will melt the upper surface of wafer 410, which will then recrystallize.

The recrystallization step is short, typically from a few seconds to a few minutes after the melting of the upper surface of the wafer.

The recrystallization step may occur in the same enclosure as that which has been used for the sintering of FIG. 17. Plungers 403 and 404 then play the role of counter-plungers 423 and 424.

The recrystallization step may be performed by other techniques. For example, an area melted by a power beam, such as a light beam, may be created at the upper surface of the wafer, and the molten area is displaced to scan the entire surface of the wafer. There also exist other methods using a scanning system, in which an area is melted across its entire thickness. According to the technique used, to keep its shape to the wafer, it may be refrained from melting the edges, which will be cut back.

FIG. 21 shows a wafer 425 corresponding to wafer 410 after recrystallization. If it has not totally melted, which is the case in FIG. 21, wafer 425 has an upper portion 426 with large grains 427 and a lower portion 428 with small grains 429. Grains 429 correspond to grains 412 of FIG. 18 and are shown in the same manner. Grains 427 have an average size d. The size of grains 427 is typically greater than or equal to 100 micrometers.

The method for manufacturing an electronic structure according to the present invention continues with a step of epitaxial deposition, as will be described in relation with FIG. 22.

In FIG. 22, wafer 425 is placed on a support, not shown, in an enclosure 430 enabling to epitaxially deposit silicon. An epitaxial silicon layer 432 is deposited on the upper surface of the wafer. The thickness of the epitaxial layer is e. The epitaxy reproduces the structure of the wafer surface, and crystals 434 form in layer 432 in continuation of crystals 427. Crystals 434 reproduce crystals 427 of the recrystallized area. Thickness e of the epitaxial area is selected to be smaller than size d of crystals 427. Typically, thickness e is on the order of from 20 to 50 micrometers. Layer 432 is doped with N-type or P-type dopants, preferably during the epitaxy step. The dopant concentration is preferably smaller than 1018 atoms/cm3. The epitaxial deposition may be performed by CVD from silane or trichlorosilane gas, by liquid phase epitaxy, by vacuum deposition or evaporation, for example, with a temperature ranging between 900 and 1,200° C. It will be avoided to exceed 1,200° C. to prevent impurity or dopant migrations from wafer 425 into the epitaxial layer. Around 1,200° C., an epitaxial deposition of some twenty micrometers generally takes approximately some twenty minutes. It should be noted that epitaxial deposition 432 is performed on a clean surface. Thus, if an oxide, for example, having a 1-nanometer thickness, has formed at the upper surface of the wafer, it is removed by reduction before the epitaxial deposition.

Liquid phase epitaxy can be carried out using different processes.

For example, silicon and a metal such as aluminum or zinc is melted. The melting occurs at a relatively low temperature, for example in the range from 800 to 1200° C. A silicon sintered wafer having a recrystallized surface is plunged into the melt. An epitaxial layer with large grains is formed on the recrystallized surface of the wafer, which leads to an electronic structure according to the present invention.

Another process to obtain a liquid phase epitaxy is to provide a melt with silicon only.

The temperature is then greater or equal to the silicon melting temperature. The sintered silicon wafer has no need to have a recrystallized surface. One surface of the sintered silicon wafer is plunged into the melt. The wafer is not completely plunged into the melt to avoid its complete melting. A zone of the surface in contact with the melt is melted and the wafer is progressively removed from the melt. Once removed, the surface recristallizes and is in the same time covered with an epitaxial layer of silicon from the melt. Such a process enables a rapid epitaxy deposition on the surface of the wafer. The control of the process enables an epitaxial layer to be obtained having the desired thickness, for example in the range from 20 to 100 micrometers.

FIG. 23 shows an electronic structure 435 according to the present invention.

In FIG. 23, structure 435 comprises an area 426 with large grains, an area 428 with small grains, and an epitaxial area 432. Area 428 may have a very small thickness, such as one micrometer. Areas 426 and 428 are heavily doped. Areas 426 and 428 are used as a support for the structure and, due to their doping, may be used as a rear electrode of the structure. The epitaxial layer is lightly doped. The function of the epitaxial area is to be used as an active layer. The epitaxial area may have a homogeneous doping, or several doping layers of different natures and concentrations. The epitaxial layer may be made of pure silicon, or of an alloy of silicon and another semiconductor material, such as germanium. The epitaxial layer may also have various layers of materials of different natures.

Structure 435 may be used to form photovoltaic cells and various other elements, such as electronic or optoelectronic components of integrated circuit type.

Among the advantages of structure 435 over prior art structures, the following should be noted:

a) Areas 426 and 428, forming the base of structure 435, may have been formed with metallurgic silicon, for example, of u-MG type, which decreases the cost of the structure.

b) Area 428, when present, is an area that may be porous and have open porosity channels. Advantage can be taken of these channels, if need be, for example to inject aluminum, which forms and/or improves the ohmic contact.

c) During the epitaxial growth, a succession of doping layers and/or of layers of different materials, adapted to the final device to be manufactured, may be formed.

Thus, the epitaxial layer may comprise a rather thick P-type doped layer, for example, with a thickness on the order of 20 micrometers, topped with an N-type doped layer of small thickness, for example, less than 1 micrometer. It should here be noted that a so-called BSF (Back Surface Field) P+ doped layer may be epitaxially deposited between area 426 and area 432. Such a BSF layer may be advantageous in some embodiments of photovoltaic cells, to prevent the recombination of the carriers created by light.

d) The method according to the present invention enables to spare technological steps, since there is no subsequent diffusion step to create the N or P layers.

Various photovoltaic cells and their embodiments will now be described based on an electronic structure according to the present invention, in relation with FIGS. 24 to 27.

In FIG. 24, a photovoltaic cell 438 according to the present invention is formed from an electronic structure 440 according to the present invention.

Structure 440 comprises a P+-type doped area 441 with small silicon grains, a P+-type doped area 442 with large silicon grains, a P-type doped layer 443, and an N or N+-type doped layer 444. Areas 441 and 442 result from the sintering of silicon powders, area 442 resulting from a surface recrystallization, performed as described previously. Layers 443 and 444 are two epitaxially-deposited silicon layers. Areas 441 and 442 have a general thickness approximately ranging from 100 to 500 micrometers, layer 443 has a typical thickness on the order of 20 micrometers, and layer 444 has a typical thickness on the order of one micrometer.

On layer 444 of structure 440 is placed an antireflection layer 445 with a surface that may have been texturized to capture as much light as possible. The antireflection layer is a very thin layer, typically on the order of 0.1 micrometer, generally of silicon nitride.

Metal pads 446 forming a comb, for example, made of aluminum, are connected to an output terminal 447. On the lower surface of cell 438, in contact with area 441, is placed a metallization layer 448, for example, made of aluminum, connected to a terminal 449 forming the other output terminal of cell 438. The forming of layer 445 and of the contacting areas is conventional and will not be specifically described.

Cell 438 operates as follows. Charge carriers are created by a photon flow at the PN junction of layers 443 and 444. The charge carriers created by light in areas 443 and 444 are carried off towards terminals 447 and 449 via the respective P+ doped and/or metallic conductive areas.

Structure 440 alone forms most of photovoltaic cell 438. Cell 438 is thus advantageous because structure 440 is inexpensive and can be formed with few technological steps. Thus, for example, the various dopings may be performed during the forming of the various areas or layers, which avoids subsequent doping steps.

It should further be noted that a significant advantage of structure 440 is the difference in microstructures between area 441 on the one hand and areas 442, 443, and 444 on the other hand. Area 441, formed of generally micronic grains, that is, of grains of dimensions ranging from one to a few micrometers, indeed has a much larger grain boundary density than the other areas, which enables to getter possible impurities introduced into the epitaxial layer(s), such as metal impurities. This gettering effect especially occurs in the structure manufacturing steps, in particular when these steps occur at high temperature, as for example for the deposition steps.

A variation of the photovoltaic cell of FIG. 24 will now be described in relation with FIG. 25.

In FIG. 25, a photovoltaic cell 450 according to the present invention comprises an electronic structure 460 according to the present invention.

Electronic structure 460 comprises an N+-type doped area 461 with small silicon grains, an N+-type doped area 462 with large silicon grains, and a P-type layer 463. Areas 461 and 462 result from the sintering of silicon powders, area 462 resulting from a surface recrystallization, performed as described previously. Layer 463 is an epitaxially-deposited silicon layer. Areas 461 and 462 have a total thickness approximately ranging from 100 to 500 micrometers, and layer 463 has a typical thickness on the order of 20 micrometers.

On layer 463 of structure 460 is placed an antireflection layer 465. Contacting areas 466 are connected to an output terminal 467 of photovoltaic cell 450. On the lower surface of cell 450, in contact with area 461, is placed a metallization layer 468 connected to a terminal 469 forming the other output terminal of cell 450. The antireflection layer and the various contacting areas of FIG. 25 are similar to the corresponding antireflection layer and contacting areas of FIG. 24 and will not be described any further.

Cell 450 of FIG. 25 operates as follows.

During the epitaxial forming of layer 463, the dopants of layer 462 slightly diffuse by forming, in the epitaxial area, an N-type doped area 470 shown in dotted lines in FIG. 25. The PN junction necessary for the cell operation here is at the level of area 470 and of layer 463. Once created by light, the charge carriers migrate towards terminals 467 and 469 of the photovoltaic cell.

Photovoltaic cell 450 has, like cell 438 of FIG. 24, all the advantages linked to the use of an electronic structure according to the present invention. It further has the following advantages.

On the one hand, since sintered support 461, 462 takes part in the junction, it is unnecessary to provide, as in FIG. 24, an N or N+-type doped epitaxial layer on the P-type epitaxial layer. Cell 450 is thus simpler to form than cell 438, which results in time and manufacturing cost savings.

On the other hand, since the PN junction is at the base of layer 463, adjacent to layer 462, the absorption of power by layer 444 of FIG. 24, which is due to the fact for the N or N+ layer to be at the surface, is avoided.

Another variation of the photovoltaic cell of FIG. 24 will now be described in relation with FIG. 26.

In FIG. 26, a photovoltaic cell 475 according to the present invention comprises an electronic structure 480 according to the present invention.

Electronic structure 480 comprises a P+-type doped area 481 with small silicon grains, a P+-type doped area 482 with large silicon grains, a layer 483 formed of several P-type doped sub-layers 483-1 to 483-n, and an N or N+-type doped layer 484. Areas 481 and 482 result from the sintering of silicon powders, area 482 resulting from a surface recrystallization performed as described previously. Areas 481 and 482 have a general thickness approximately ranging from 100 to 500 micrometers. Layer 484 has a typical thickness on the order of one micrometer.

Layer 483 is formed of sub-layers 483-i, with i ranging from 1 to n, which have been epitaxially deposited and P-type doped. Each sub-layer 483-i is formed of a material having chemical formula SixGe1-x, where the value of x may range from 0 to 1. Thus, sub-layer 483-1 in contact with area 482 may be pure germanium, while the next sub-layers are silicon and germanium alloys with an increasing silicon content, to reach pure silicon in sub-layer 483-n. Layer 483 has a typical total thickness approximately ranging from 20 to 50 micrometers. Preferably, the number of sub-layers 483-i is limited, for example, equal to three or four. Three sub-layers 483-1 to 483-3 have been shown in FIG. 26. Each of the layers may be doped during the deposition with variable dopant concentrations. In addition to electronic structure 480, photovoltaic cell 475 comprises an antireflection layer 485, metallization pads 486 connected to a first terminal 487 of the cell, as well as a rear metallization layer 488 connected to a second terminal 489 of the cell. Since these elements have been described and have an analog function, they will not be discussed any further.

In addition to the advantages of using an electronic structure according to the present invention (low cost, manufacturing simplicity, etc.), the photovoltaic cell of FIG. 26 is advantageous since it has a greater efficiency than cell 438 of FIG. 24.

Indeed, the energy gaps of silicon, germanium, and the silicon-germanium alloys being different, more electron-hole pairs are created since the photon power is better used than in the case of pure silicon. In particular, the infrared portion of the solar spectrum is converted with a greater efficiency if a structure where the layers contain more silicon on the surface exposed to light and more germanium in the underlying layer is formed. Further, the use of germanium enables to have a higher carrier mobility and a better conductivity, as well as an enhanced ohmic contact with the conductive areas.

FIG. 27 shows another embodiment of a photovoltaic cell according to the present invention.

In FIG. 27, a photovoltaic cell 490 comprises an electronic structure 495 according to the present invention. Structure 495 comprises a lower support 500 and an upper layer 502.

Lower support 500 originates from a sintered silicon wafer doped as described in FIG. 19. Thus, support 500 comprises N+-type doped areas 505, alternating with P+-type doped areas 507. Areas 505 typically have a width on the order of two millimeters and areas 507 typically have a width on the order of one millimeter. Between areas 505 and 507 are located areas 508 that may have been made insulating by the addition of an insulator into the porosity channels. Support 500 has large grains, of a size typically greater than or equal to 100 micrometers, at its upper surface in contact with layer 502. Such large grains result from a surface recrystallization and have not been shown in FIG. 27 to avoid overloading the drawing. Support 500 generally has small grains in its lower portion, which has remained porous. The thickness of support 500 approximately ranges from 100 to 500 micrometers, as in the case of the previously-described cells.

Layer 502 results from the epitaxial deposition of silicon on the recrystallized surface of support 500. Layer 502 is P-type doped.

At the base of layer 502, in contact with support 500, N-type doped areas 510 and P-type doped areas 512 can be found. Areas 510 are adjacent to areas 505 and areas 512 are adjacent to areas 507. Areas 510 and areas 512 have been obtained during a diffusion step which has diffused the dopants of areas 505 and 507 into layer 502. The diffusion may be obtained by heating at a temperature on the order of 900° C. after the epitaxial deposition of layer 502. A diffusion also occurs during the epitaxial deposition of layer 502 and a subsequent diffusion step may result being unnecessary. On the upper surface of layer 502 is placed an antireflection layer 514 similar to the antireflection layer of the previously-described cells.

On the lower surface of structure 495 are placed pads 515 opposite to areas 505 and pads 517 opposite to areas 507. Pads 515 and 517 are metallic, for example, made of aluminum. Pads 515 are connected to a terminal 520 and pads 517 are connected to a terminal 530. Terminals 520 and 530 form the two output terminals of cell 490.

Photovoltaic cell 490 operates as follows.

The PN junction is located at the level of areas 510 and of epitaxial layer 502. Areas 507 are narrower than areas 505 since their function is different. Indeed, areas 507 are used, via areas 512, to promote the ohmic contact with epitaxial area 502. N+-type doped areas 505 are also used to promote the ohmic contact with metal areas 515.

Photovoltaic cell 490 has, on the one hand, all the advantages due to the presence of an electronic structure according to the present invention.

On the other hand, in cell 490, all electric contacts are made on the lower cell surface. There is no collector comb at the cell surface exposed to the radiation. As a result, a larger surface area is available to receive the radiation, which brings about an improved efficiency of the cell.

Further, cell 490 has no specific surface dopings, like layer 444 of FIG. 24, which are generally quite high and absorb part of the light.

It should be noted that photovoltaic cell 490 cannot be formed with a conventional substrate made of single-crystal silicon or polysilicon, since a single-crystal silicon or polysilicon substrate does not enable to perform the doping illustrated in FIG. 19.

Various embodiments with different variations have been described hereabove. It should be noted that those skilled in the art may modify or combine various elements of these various embodiments and variations without showing any inventive step.

For example, in cells 438, 450, and 490, the epitaxial layer may comprise several sub-layers of variable formulas SixGe1-x and of variable doping as in the case of cell 475.

Also, the various thicknesses and magnitudes have been given as an indication only. For example, due to the low cost of sintering, the supports of the structures or cells according to the present invention may be thicker, for example, with a thickness ranging from one to several millimeters if desired.

Thus, the thickness of the epitaxial layer has been described as approximately ranging from 20 to 50 micrometers. Of course, the epitaxial layer may be thinner, for example, of 10 micrometers, or thicker, for example up to 100 or 150 micrometers.

Of course, in all the previously-described examples of electronic structures or of cells, the nature of the dopants may be inverted. For example, the P or P+-type doped areas of a structure or cell may be replaced with N or N+-type doped areas, the N or N+-type doped areas of the structure or of the cell being replaced with P or P+-type areas.

Also, support wafer 410 or 425 can be without doping. For example, in such a case, the contacts of a photovoltaic cell made with such a support will be placed either on the front face of the cell or on the rear face of the cell, metalized holes traversing the support and enabling the contact with the epitaxial active layer.

It should also be noted that the structures of the present invention, which enable to form photovoltaic cells, may be used in other devices, the epitaxial area being used as an active area. Examples of such applications for example are integrated circuits of electronic or optoelectronic type.

Embodiments of a photovoltaic module according to the present invention will now be described in relation with FIG. 28A to 30C.

For clarity, the same elements may have been designated with the same reference numerals in the different drawings and, further, as usual in the representation of integrated circuits, the various drawings are not to scale.

The photovoltaic modules according to the present invention comprise a support formed by sintering of silicon powders.

A sintered silicon wafer is different from a single-crystal, polycrystalline, or multicrystalline silicon wafer since it is less dense and has a non-zero porosity. Indeed, a conventional wafer made of single-crystal silicon, polysilicon, or multicrystalline silicon results from a melt and has no porosity at all, while a sintered silicon wafer always is porous, except, possibly, in areas where it would have been melted, for example, during a subsequent anneal.

A first embodiment of a photovoltaic module according to the present invention will be described in relation with FIGS. 28A to 28G.

FIG. 28A shows a parallelepipedal sintered silicon support 601. Support 601 has a typical thickness e approximately ranging from 400 μm to 1 mm. Of course, support 601 may be thicker, with a thickness for example ranging up to a few millimeters. Length L and the width of support 601 may be quite large, on the order of several tens of centimeters, or even more. For example, support 601 has a rectangular surface having a dimension of 400 by 700 millimeters.

Support 601 has been obtained by sintering of silicon powders. The powders used for example have a micrometric size and support 601 has silicon grains of micrometric size. The powder sintering conditions (temperature, pressure, duration, etc.) are controlled and support 601 has a determined porosity. For example, the porosity ranges from a few percents to 30 or 50 percents. The porosity of support 601 may be open or closed.

It will be reminded that the porosity is said to be open or interconnected when the pores or porosity channels are interconnected and cross the support. The porosity is said to be closed or non-interconnected when all pores are not interconnected and the pores which emerge on a surface do not reach the other surface.

Unlike dense silicon supports resulting from a melt, the porosity of support 601 enables it to be permeable to a gas, to a liquid, or to a viscous material, which property will be exploited hereafter.

In FIG. 28A, support 601 is P+-type doped, that is, with a dopant concentration greater than or equal to 1018 atoms per cm3. Support 601 may be doped in various ways. For example, dopants may be introduced via the porosity channels after the support has been formed. Also, dopants may have been mixed with the silicon powders before sintering or the sintered powders may have been previously doped.

The fact for support 601 to be porous enables to have the dopants penetrate rapidly down to a great depth, which is an advantage over dense non-porous silicon. For example, if a P or P+-type area is desired to be doped in dense silicon by means of boron, the boron penetration is slow, on the order of 0.1 μm at 1,000° C. for one hour. In the present invention, support 601 can be rapidly doped by diffusion throughout its entire volume and at lower temperature.

In FIG. 28B, support 601 is topped with a layer 603 and with a layer 605.

Layer 603 lies on support 601 and is made of P-type doped silicon, that is, with a dopant concentration smaller than 1018 atoms per cm3. Layer 603 is rather thick, typically on the order of 20 μm. Of course, layer 603 may have various thicknesses, for example from 10 to 50 μm. Layer 603 is made of dense non-porous silicon. For example, it is a single-crystal silicon layer, which is glued or results from an epitaxial deposition in gas or liquid phase. In this latter case, a previous layer may have been deposited on the support, and then recrystallized, or the support may have been recrystallized at the surface. The aim of the recrystallization is to increase the size of the grains and make them, for example, millimetric or centimetric.

Layer 605 lies on layer 603. Layer 605 is made of N-type doped silicon, with a dopant concentration lower than 1018 atoms per cm3, or of N+-type doped silicon, with a dopant concentration greater than or equal to 1018 atoms per cm3. Layer 605 is for example obtained by coating layer 603 with a material containing phosphorus and by performing an anneal. Layer 605 is very thin, typically on the order of 0.1 micrometer. A PN junction is present at the interface of layers 603 and 605.

In FIG. 28C, trenches 607 are formed by a laser to separate areas 609 formed of a portion of layers 603 and 605. Areas 609 may have the shape of a square, of a rectangle, or any other shape, preferably tileable. Areas 609 may also be strips extending over all or part of the width of support 601. Areas 609 may have any dimensions, but these will preferably be of several centimeters. For example, areas 609 are squares with a side ranging from 2 to 10 centimeters.

Trenches 607 are sufficiently deep such that layer 603 is totally removed between areas 609. Trenches 607 may stop on support 601 or be deeper and penetrate into support 601. Trenches 607 may be narrow, for example, with a 100-μm width.

FIG. 28D illustrates an oxidation step. This oxidation step is remarkable in that it has no equivalent in the state of the art.

In FIG. 28D, a layer 611 is deposited on the lower surface of support 601. Layer 611 prevents any gaseous, liquid, or viscous agent from penetrating through the lower surface of support 601. Layer 611 for example is a 0.1-μm thick silicon nitride layer. Layer 611 may also be formed of a silicon nitride layer lying on a thinner silica layer, for example, of 25 nanometers, to limit the stress exerted by the silicon nitride layer.

After deposition of layer 611, oxygen, for example in the form of water vapor H2O, of dioxygen O2 or of a mixture of dioxygen and water vapor, is applied to the structure. The oxygen or agent containing the oxygen penetrates into support 601 through the porosity channels at the level of trenches 607. The oxygen path is symbolized in FIG. 28D by arrows bearing reference 02.

Oxidized areas 614 are formed under trenches 607. The process is controlled so that areas 614 reach the lower surface of support 601, without joining. Thus, areas 614 delimit P+-type doped wells 618, insulated from one another and joining the lower surface of support 601. Layer 611 is preferably removed after the oxidation process.

The oxidation of support 601 is fast since the oxidizing fluid penetrates into the porosity channels and rapidly oxidizes the silicon to form a generally partially oxidized material SiOx in FIG. 28D. The oxidation of silicon, even partial, makes the oxidized area insulating.

It should be noted that oxide is generally formed on layer 605. Due to the fact that layer 605 is made of dense silicon, the oxide thickness which is formed on layer 605 is very small. This oxide layer may be subsequently removed or left and be used afterwards as a passivation layer and/or as an antireflection layer of the future photovoltaic cell.

It should also be noted that the oxidation described in FIG. 28D is performed with a support having an open porosity. The oxidation step may also be carried out if the support has a closed porosity. In this case, layer 611 is not formed and oxygen also penetrates through the lower surface of support 601. The process is controlled so that the areas oxidized from trenches 607 join or overlap the oxidized areas from the lower surface of support 601. P+ wells insulated from one another by oxidized areas are also created, but they do not reach the lower surface of support 601.

To complete the photovoltaic cells, a collector comb must be placed on layer 605 of each area 609 and passivation and/or antireflection layers may be formed. These steps are conventional and will not be described herein. It should only be noted that the placing of the collector combs may be performed on the oxide layer generated in the oxidation step, an anneal enabling the conductive material of the comb to cross the oxide layer and ensure the electric contact with N-type doped layer 605.

The photovoltaic cells may be connected in various ways. FIGS. 28E to 28G illustrate examples to connect the cells in series.

In FIG. 28E, combs have been formed on areas 609 of FIG. 28D, areas 609 now forming photovoltaic cells 620.

Conductive vias 624 cross support 601 in oxidized portions 614. The comb of a cell 620, not shown, is connected to the via 624 adjacent to the cell by a connection 626. At the rear surface of support 601, a metallization 628 connects via 624 of a cell 620 to the P+ well of the next cell 620.

The P+ well of the first cell is connected to an external terminal forming the + terminal of the photovoltaic module and via 624 of the last cell is connected to an external terminal forming the − terminal of the photovoltaic module. It is of course possible not to form last via 624 and to connect the − terminal of the module to the comb of the last cell.

Several vias per cell may be provided, the number of vias being a function of the maximum intensity likely to be provided by the cells.

It should be noted that if the P+ wells do not reach the lower surface of support 601, additional conductive vias will be provided to connect metallization 628 to the P+ well, to connect the cells in series.

FIGS. 28F and 28G show another embodiment of a connection of cells 620 in series.

In FIG. 28F, trenches 645 are formed on one of the edges of cells 620.

Trenches 645 stop at the surface of support 601 and expose an area 647 of the P+ doped well.

In FIG. 28G, a conductive connection 648, for example, a metallization, connects the comb, not shown, of each cell 620 to area 647 of the next cell. The cells are thus connected in series. The + terminal of the module is connected to area 647 of the first cell and the − terminal of the module is connected to the comb of the last cell.

FIG. 28H is a top view of a photovoltaic module 650 according to the present invention.

Module 650 has been formed according to a method described in relation with FIGS. 28A to 28G. Module 650 thus comprises many cells 654 integrated on a sintered silicon support. Cells 654 are connected in series.

Module 650 may comprise an area 656 on which no photovoltaic cell has been formed. Area 656 may for example comprise integrated electronic regulation or security circuits, support 601 behaving as a substrate for these circuits.

Area 656 may comprise electronic components or a circuit comprising one or several diodes enabling to short-circuit a group of cells which would be shadowed. Such circuits do not exist as integrated to a photovoltaic module in prior art, and are generally at the module periphery.

The specific components used to protect or to control the operation of one or of a group of cells may be formed beforehand on single-crystal semiconductor wafer elements and placed on support 601 or on polycrystalline semiconductor layers deposited on support 601. An inverter for generating an AC-voltage may also be integrated.

The components integrated to the module may for example be sensors controlling the temperature of the cells or more complex circuits comprising systems for regulating the voltages and currents generated by the module.

Of course, before it is marketed, module 650 may be protected by conventional means, for example, by a polymer film and a glass plate on its front surface, intended to be exposed to sunlight (called upper surface in the foregoing), and/or a polymer film and a glass plate or a polymer or ceramic plate on its rear surface.

Module 650 may deliver any output voltage, each photovoltaic cell approximately delivering a 0.6-volt voltage. For example, the voltage delivered by the module may range from a few volts to several hundreds of volts. The intensity that module 650 can deliver is scalable according to the size of the cells or to their connection, some cell being connectable in parallel. The size of the cells may vary from a few square centimeters to several hundreds of square centimeters.

Photovoltaic module 650 may be large, the module size being selected according to the desired application. The size of the module may for example range from 0.25 square meter to one square meter or more. The delivered power may be on the order of 150 watts per square meter.

Module 650 is not necessarily planar, sintering techniques enabling to form curved supports.

A second embodiment of the photovoltaic module will now be described in relation with FIGS. 29A to 29G.

In this second example, all connections are formed from the back and the combs are buried, which enables to decrease the shadowing created by connections which would be deposited on the front surface, thus improving the cell efficiency.

In FIG. 29A, a support 700 is formed by sintering of silicon powders, such as support 601 of FIG. 28A. However, in FIG. 29A, support 700 is not doped and is thus insulating.

P+-doped areas 704 and N+-type doped areas 706 are laid on support 700. Areas 704 and 706 may for example result from the deposition of a material containing boron or phosphorus, or result from the deposition of silicon layers containing boron or phosphorus. Although areas 704 and 706 may have any dimension and shape, areas 704 and areas 706 are preferably interdigited and the space separating them is small, for example, on the order of from 10 to 100 μm. The P+ doped areas are preferably narrower than the N+ doped areas. For example, areas 704 have a width of 100 μm and areas 706 have a 500-μm width.

In FIG. 29B, the structure is annealed and the dopants of areas 704 and 706 migrate into support 700. Thus, in FIG. 29B, P+-type doped areas 714 are present under areas 704 and N+-type doped areas 716 are present under areas 706. If desired, a short oxidation step may be carried out to make sure that areas 714 and 716 have a good electric insulation with respect to one another.

FIGS. 29C and 29D illustrate steps of the forming of the absorber of the future photovoltaic cells.

In FIG. 29C, a P-type doped silicon layer 720 is deposited, for example, by CVD, on the structure of FIG. 29B. Layer 720 has a relatively low thickness, for example, 2 μm. After deposition thereof, layer 720 is recrystallized, for example, by ZMR (“Zone Melting Recrystallization”), that is, by scanning of a surface-molten area, to increase the size of the grains, which become centimetric in the scanning direction.

In FIG. 29D, a P-type doped layer 722 is deposited by epitaxy on layer 720. Epitaxial layer 722 has a thickness on the order of 20 μm. Of course, it may have another thickness, for example, from 10 to 50 μm. Layer 722 has grains 724 in continuity with the grains of layer 720. Grains 724 cross the entire layer 722, which enhances the efficiency of the future cell by decreasing the trapping of the carriers.

In FIG. 29E, trenches 726 are for example made by laser to separate the future cells. Trenches 726 reach support 700. Trenches 726 totally surround future cell 730. Although, in FIG. 29E, trenches 726 only insulate a pair of adjacent areas 704 and 706, in practice, since the cells are centimetric, trenches 726 may insulate several tens of pairs of P+ and N+ areas. This has not been shown in FIG. 29E for clarity.

Then, an antireflection layer and a passivation layer are deposited on the cells. Of course, a single layer may be used as an antireflection layer and as a passivation layer. The antireflection and/or passivation layers are not shown in FIG. 29E.

It should be noted that the PN junction of cells 730 is at the interface of N+ areas 706 and of the absorber formed by layers 720 and 722. Areas 706 are also used to carry off the holes generated by the photons, and areas 704 are used to drain off the electrons.

FIG. 29F illustrates the connection of cells 730 in series.

In FIG. 29F, conductive vias 732 join the rear surface of support 700 and P+ doped areas 714. Conductive vias 734 join the rear surface of support 700 and N+ doped areas 716. Several vias 732 and 734 per cell may be necessary to conduct the maximum intensity likely to be provided. A conductive connection 736 such as a metallization connects vias 732 of a cell to vias 734 of the next cell. As in FIG. 29E, cells 730 are shown with a single P+ area 714 and a single N+ area 716, for clarity. In practice, all the P+ areas 714 of a same cell are interconnected and all the N+ areas 716 of a same cell are interconnected.

The cells are thus connected in series. They form a photovoltaic module 750. The + terminal of module 750 is connected to P+ area 714 of the first cell and the − terminal of module 750 is connected to N+ area 716 of the last cell.

It should be clear that cells may also be connected in parallel. Generally, for equal intensities and voltages, a module with a large number of small cells may be preferred to a module with a small number of large cells, to decrease the current crossing each cell.

The operation of the module, such as that of the cells, is within the abilities of those skilled in the art and will not be described any further.

FIG. 29G shows the front surface of module 750, exposed to sunlight. Nine cells 730 are shown in FIG. 29G. The collector combs correspond to areas 704 and 706 and are buried. For clarity, a single pair of areas 704 and 706 per cell has been shown in FIG. 28G. It should be clear that in practice, each cell may comprise more than one pair of areas 704 and 706.

To show that the present invention may have many alterations and modifications without departing from the scope of the present invention, a third example of a photovoltaic module according to the present invention will now be described in relation with FIGS. 30A to 30C, where all connections are on the front surface.

In FIG. 30A, a support 800 is topped with a P+ doped layer 810. Layer 810 supports a P-type doped layer 820. An N-type doped layer 830 is present on layer 820.

Support 800 is made of sintered silicon. Support 800 is similar to previously-described supports 601 or 700. Support 800 may indifferently be doped or undoped.

Layer 810 may be thin (a few μm) and have been deposited and recrystallized to comprise grains of significant size, typically millimetric or centimetric. Layer 810 may also be thicker, for example, from 10 to 100 μm, and have been formed by annealing the upper surface of support 800 and by making it P+-type doped, except if the support has already been P+ doped.

Layer 820 may have been deposited by epitaxy on layer 810 and have large grains in continuity with the grains of layer 810. Layer 820, intended to form the cell absorber, has a typical thickness ranging between 10 and 50 μm.

Layer 830 is thin, typically on the order of 1 micrometer. Layer 830 may have been formed like layer 605 of FIG. 28B. A PN junction is present at the interface of layers 820 and 830.

In FIG. 30B, cells 840 are insulated from one another by trenches 850. Trenches 850 are formed of a portion 852 and of a portion 854. Portion 852 stops at the interface of layers 810 and 820. Portion 854 is deep enough for layer 810 to be interrupted, whether it comes from a deposited layer or from a surface doping of support 800. Thus, a flat area 856 exposing a portion of P+ layer 810 appears at the edge of each cell 840.

If support 800 is made of doped silicon, an oxidizing agent is applied via trenches 850 to avoid any electric contact of cells 840 via support 800. Since the oxidation step has been described in relation with FIG. 28D, it will not be detailed. The oxidation step is not essential if the sintered silicon support is not doped and if layer 810 has been deposited, but it could however be maintained in all cases for security reasons.

Conductive combs, not shown, are formed on the front surface of cells 840.

In FIG. 30C, electric connections 860 are formed to connect flat area 856 of a cell 840 to the collector comb of the next cell.

The photovoltaic module is completed by the addition of passivation and/or antireflection layers, then encapsulated before being put on the market. These steps will not be detailed. The measures to be taken to avoid possible short-circuits which could occur between layers 820 and 830 of a same cell due to connection 860 have not been detailed either, it being within the abilities of those skilled in the art to solve these problems when they are posed.

It should be noted that the embodiment of FIGS. 30A to 30C is particularly well adapted to the forming of cells in the form of strips extending across the entire width of the module. Indeed, the cell separation is then performed in a particularly simple manner, since simple trenches extending from one edge to the other of the support have to be made. The strips may be narrow, for example with a 1-centimeter width, especially if the module must provide a high voltage.

As a conclusion, is should be noted that the use of a sintered silicon support to form photovoltaic modules according to the present invention has many advantages.

For example, sintered silicon supports are cheap, especially since they may be formed from low-purity silicon powders, possibly from metallurgical grade silicon.

Sintered silicon supports may have much large dimensions than current single-crystal silicon, multicrystalline silicon, or polysilicon wafers. Sintered silicon supports are not necessarily planar.

Also, the technological steps to form cells on a sintered silicon support are often quite simple. For example, in the present invention, the electric insulation of the wells supporting the cells is technically performed by penetration of an oxidizing agent into the porosity channels of the support.

Specific embodiments of the present invention have been described. It should be clear that these examples are not limiting. Various alterations, modifications, and improvements will readily occur to those skilled in the art, who may combine various elements of these various embodiments and variations without showing any inventive step.

For example, the dopings of the various layers and areas described in the above examples are not limiting. It is thus equivalent to invert all the indicated dopings.

Also, the method steps are given as an example only. It will be within the abilities of those skilled in the art to modify these steps, and even to invert their order, without departing from the scope of the present invention.

Generally, photovoltaic modules according to the present invention comprise a sintered silicon support and photovoltaic cells. It should be understood that whatever the shape, the structure, and/or the steps used to form the module and/or the photovoltaic cells of the module, any photovoltaic module comprising a sintered silicon support falls within the scope of the present invention.

Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto. 

What is claimed is:
 1. A structure comprising a first support wafer made of sintered silicon, the first support wafer comprising porosity channels formed therein via a sintering process, and a second layer of single-crystal silicon, wherein the porosity channels are interconnected and exit outwards, and contain a doping element or a conductive material.
 2. The structure of claim 1, comprising a layer forming a diffusion barrier between the first support wafer and the second layer.
 3. The structure of claim 2, wherein the layer forming a diffusion barrier is a silica, silicon nitride, and/or silicon carbide layer.
 4. The structure of claim 3, wherein the layer forming a diffusion barrier has a thickness smaller than ten nanometers.
 5. The structure of claim 2, wherein the layer forming a diffusion barrier has a thickness smaller than ten nanometers.
 6. The structure of claim 1, comprising a layer forming an insulator between the first support wafer and the second layer.
 7. The structure of claim 6, wherein the layer forming an insulator is a silica, silicon nitride, and/or silicon carbide layer.
 8. The structure of claim 7, wherein the layer forming an insulator has a thickness greater than ten nanometers.
 9. The structure of claim 6, wherein the layer forming an insulator has a thickness greater than ten nanometers.
 10. The structure of claim 6, wherein holes cross the first support wafer and the layer forming an insulator.
 11. The structure of claim 1, wherein the first support wafer has a thickness greater than 50 micrometers and/or the second layer has a thickness ranging between one and 50 micrometers.
 12. The structure of claim 1, wherein the silicon of the first support wafer is not pure silicon.
 13. The structure of claim 1, wherein holes cross the first support wafer. 